PIC18F248-E/L MICROCHIP [Microchip Technology], PIC18F248-E/L Datasheet - Page 299
PIC18F248-E/L
Manufacturer Part Number
PIC18F248-E/L
Description
28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F248-EL.pdf
(402 pages)
- Current page: 299 of 402
- Download datasheet (8Mb)
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Clear f
[ label ] CLRF
0
a
000h
1
Z
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be selected
as per the BSR value (default).
1
1
CLRF
Read
0110
Q2
f
[0,1]
=
=
Z
255
f
0x5A
0x00
101a
Process
FLAG_REG
Data
f [,a]
Q3
ffff
register ‘f’
Write
Q4
ffff
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WDT Counter
WDT Counter
WDT Postscaler
TO
PD
Q1
operation
Clear Watchdog Timer
[ label ] CLRWDT
None
000h
000h
1
1
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits TO
and PD are set.
1
1
CLRWDT
0000
No
Q2
TO,
PD
PIC18FXX8
WDT,
WDT postscaler,
=
=
=
=
=
0000
Process
?
0x00
0
1
1
Data
Q3
DS41159E-page 297
0000
operation
No
Q4
0100
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