MC68HC705T16 MOTOROLA [Motorola, Inc], MC68HC705T16 Datasheet - Page 47

• Manufacturer Part Number: MC68HC705T16
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: MOTOROLA [Motorola, Inc]

contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($12), the counter transfer is inhibited until the LSB ($13)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($13) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
5.1.4
The TCR is a read/write register containing five control bits. Four bits control interrupts associated
with each of the four flag bits found in the Timer Status register. The other bit controls which edge
is significant to the input capture edge detector. The Timer Control register and the free-running
counter are the only sections of the timer affected by reset.
Definition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
OC0IE - Output Compare Interrupt Enable
OC1IE - Output Compare Interrupt Enable
TOVFIE - Timer Overflow Interrupt Enable
IEDG - Input Edge
MC68HC05T16
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Address
$10
Timer Control Register (TCR)
–
–
–
–
–
bit 7
ICIE
Input Capture interrupt enabled.
Input Capture interrupt disabled.
Output Compare 0 interrupt enabled.
Output Compare 0 interrupt disabled.
Output Compare 1 interrupt enabled.
Output Compare 1 interrupt disabled.
Timer Overflow interrupt enabled.
Timer Overflow interrupt disabled.
TCAP is positive-going edge sensitive.
TCAP is negative-going edge sensitive.
OC0IE
bit 6
OC1IE
bit 5
TOVFIE
bit 4
TIMERS
bit 3
bit 2
IEDG
bit 1
bit 0
0000 0000
on reset
State
MOTOROLA
TPG
5-5
5