LAN83C185_03 SMSC [SMSC Corporation], LAN83C185_03 Datasheet - Page 29

• Manufacturer Part Number: LAN83C185_03
• Description: High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
MDIO
MDC
MDI0
MDC
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
The timing relationships of the MDIO signals are further described in
Management Interface (SMI) Timing," on page
Preamble
Preamble
32 1's
32 1's
Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle
Figure 4.4 MDIO Timing and Frame Structure - READ Cycle
Start of
Start of
Frame
0
0
Frame
1
1
1
0
Code
Code
OP
OP
0
1
Figure 4.4
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address
PHY Address
Data To Phy
Read Cycle
Write Cycle
and
DATASHEET
Figure
Data To Phy
21
4.5.
Register Address
Register Address
47.
Around
Around
Turn
Turn
D15
D15
D14
D14
Section 6.1, "Serial
Data From Phy
Data
Data
Rev. 0.6 (12-12-03)
...
...
...
...
D1
D1
D0
D0