LAN83C185_03 SMSC [SMSC Corporation], LAN83C185_03 Datasheet - Page 43

• Manufacturer Part Number: LAN83C185_03
• Description: High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
18.4:0
20.15
20.14
20.13:11
20.10
20.9:5
20.4:0
ADDRESS
ADDRESS
ADDRESS
21.15:0
ADDRESS
22.15:0
READ
WRITE
Reserved
TEST MODE
READ
ADDRESS
WRITE
ADDRESS
PHYAD
READ_DATA
READ_DATA
NAME
NAME
NAME
NAME
Table 5.43 Register 18 - Special Modes (continued)
When setting this bit to “1”, the content of the register
that is selected by the READ ADDRESS will be
latched to the TSTREAD1/2 registers. This bit is self-
cleared.
When setting this bit to “1”, the register that is selected
by the WRITE ADDRESS is going to be written with
the data from the TSTWRITE register. This bit is self-
cleared.
Enable the Testability/Configuration mode:
0 - Testability/Configuration mode disabled
1 - Testability/Configuration mode enabled
The address of the Testability/Configuration register
that will be latched into the TSTREAD1 and
TSTREAD2 registers
The address of the Testability/Configuration register
that will be written.
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to
PHYAD[4:0]," on page 41
When reading registers with a size of less then 16
bits, this register contain the register data, starting
from bit 0.
When reading registers with a size of more then 16
bits, this register contain the less significant 16 bits of
the register data.
When reading registers with a size of less then 16
Table 5.45 Register 21 - TSTREAD1
Table 5.46 Register 22 - TSTREAD2
bits, this register clears to zeros.
When reading registers with a size of more then 16
bits, this register contains the most significant bits of
the register data, starting from the 16
Table 5.44 Register 20 - TSTCNTL
Section 5.4.9.1, "Physical Address Bus -
DATASHEET
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
35
for more details.
th
bit.
RO
RO
RW,
NASR
RW
RW
RW
RW
RW
MODE
MODE
MODE
MODE
Rev. 0.6 (12-12-03)
DEFAULT
0
DEFAULT
0
DEFAULT
PHYAD
DEFAULT
0
0
0
0
0