LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 116

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
6.1.2
REGISTER NAME
MAC_CSR_DATA
MAC_CSR_CMD
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
BYTE_TEST
FREE_RUN
PMT_CTRL
GPIO_CFG
E2P_DATA
RX_DROP
GPT_CFG
GPT_CNT
AFC_CFG
E2P_CMD
IRQ_CFG
FIFO_INT
HW_CFG
INT_STS
RX_CFG
TX_CFG
ENDIAN
ID_REV
INT_EN
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9115, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
Table 6.1 Read After Write Timing Rules
FOLLOWING ANY WRITE CYCLE
MINIMUM WAIT TIME FOR READ
DATASHEET
(IN NS)
1155
495
330
165
165
165
165
165
165
495
165
165
495
165
660
165
165
165
165
165
0
0
0
0
116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Table 6.2, "Read After Read Timing
READS (ASSUMING T
NUMBER OF BYTE_TEST
165NS)
0
3
2
1
0
1
1
1
1
1
0
3
7
1
1
3
1
4
0
1
1
1
1
1
Rules". The host
SMSC LAN9115
CYCLE
Datasheet
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