LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 73

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
5.3.1
5.3.2
BITS
BASE ADDRESS
31-16
BITS
31:24
23-15
15-0
+ OFFSET
B8h - FCh
ACh
B0h
B4h
DESCRIPTION
Chip ID. This read-only field identifies this design
Chip Revision. This is the current revision of the chip.
DESCRIPTION
Interrupt Deassertion Interval (INT_DEAS). This field determines the
Interrupt Deassertion Interval for the Interrupt Request in multiples of 10
microseconds.
Writing zeros to this field disables the INT_DEAS Interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-
zero value is written to the INT_DEAS field, any subsequent interrupts
will obey the new setting.
Note:
Reserved
ID_REV—Chip ID and Revision
This register contains the ID and Revision fields for this design.
IRQ_CFG—Interrupt Configuration Register
This register configures and indicates the state of the IRQ signal.
Offset:
Offset:
The Interrupt Deassertion interval does not apply to the PME
interrupt.
Table 5.1 LAN9115 Direct Address Register Map (continued)
RESERVED
E2P_DATA
E2P_CMD
AFC_CFG
SYMBOL
CONTROL AND STATUS REGISTERS
50h
54h
DATASHEET
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
Reserved for future use
73
REGISTER NAME
Size:
Size:
32 bits
32 bits
TYPE
R/W
TYPE
RO
RO
RO
Revision 1.1 (05-17-05)
00000000h
00000000h
00000000h
DEFAULT
DEFAULT
DEFAULT
0001h
0115h
-
0
-