MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 102

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

NF — Noise Error Flag
FE — Framing Error Flag
7.8.5
The baud rate register (BAUD) is used to set the bit rate for the SCI system. Normally this register
is written once, during initialization, to set the baud rate for SCI communications. Both the receiver
and the transmitter use the same baud rate which is derived from the MCU bus rate clock. A two
stage divider is used to develop custom baud rates from normal MCU crystal frequencies so it is not
necessary to use special baud rate crystal frequencies.
TCLR — Clear Baud Rate Counters (for test purposes only)
SCP1, SCP0 — Serial Prescaler Select bits
MOTOROLA
7-12
Baud Rate Register (BAUD)
RESET:
This bit is set if there is noise on a “valid” start bit, any of the data bits, or on the stop bit.
The NF bit is set during the same cycle as the RDRF bit but does not get set in the case
of an overrun (OR).
This bit is set when the word boundaries in the bit stream are not synchronized with the
receiver bit counter (generated by the reception of a logic zero bit where a stop bit was
expected). The FE bit reflects the status of the byte in the receive data register and the
transfer from the receive shifter to the receive data register is inhibited in the case of
overrun. The FE bit is set during the same cycle as the RDRF bit but does not get set in
the case of an overrun (OR). The framing error flag inhibits further transfer of data into
the receive data register until it is cleared.
READ:
WRITE:
This bit is disabled and remains low in any mode other than test or bootstrap mode. Reset
clears this bit. While in test or bootstrap mode, setting this bit causes the baud rate
counter chains to be reset. The logic one state of this bit is transitory and reads always
return a logic zero. This control bit is intended only for factory testing of the MCU.
READ:
WRITE:
The E-clock is divided by the factors shown in Table 7-1. This prescaled output provides
an input to a divider which is controlled by the SCI rate select bits (SCR2 – SCR0).
$102B
TCLR
Always returns 0.
Only while SMOD = 1 (test or bootstrap mode)
Any time
Any time
7
0
SERIAL COMMUNICATIONS INTERFACE
6
0
0
SCP1
5
0
SCP0
4
0
RCKB
3
0
SCR2
U
2
SCR1
U
1
SCR0
U
0
BAUD
MC68HC11G5