MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 123

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
There are three available clocks (A, B and S). Clock A can be software-selected to be E, E/
2, E/4 or E/8. Clock B can be software selected to be E, E/2, E/4,..., E/128. The block diagram
of Figure 10-1 depicts the three different clocks and how the scaled clock is created.
The scaled clock (S) uses clock A as an input and divides it with a reloadable counter. This counter
is compared with a user programmable scale value (in the PWSCAL register). When they match,
a pulse is output and the 8-bit counter is reset. The output signal from this circuit is then divided by
two to give clock S. The rates available for clock S, therefore, are software selectable to be clock A
divided by 2 down to clock A divided by 512 in increments of 2.
Each PWM timer channel can be driven by one of two clocks, selected in software: Channels 1 and 2
can use clock A or clock S; Channels 3 and 4 can use clock B or clock S.
Writing to PWSCAL causes the 8-bit counter to be reset to $00. Otherwise, when changing from a
low rate to a higher rate, it would be possible for the counter to miss the new value and have to go
all the way to $FF and wrap back around before counting at the proper rate. Forcing the counter to
$00 every time it is written prevents this.
The PWCLK register contains two control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Concatenation of channels 3 and 4 is controlled by the CON34
bit; similarly, channels 1 and 2 are concatenated using the CON12 bit.
When channels 3 and 4 are concatenated, channel 3 registers become the high order bytes of the
double byte channel. Reading the counter high order byte causes the low order byte to be latched
for one cycle, to guarantee that double byte reads will be accurate. Writing to the low byte of the
counter (channel 4) causes the entire counter to be reset. Writing to the upper byte of the counter
has no effect.
Similarly, when channels 1 and 2 are concatenated, channel 1 registers become the high order bytes
of the double byte channel.
The 16-bit duty register and period register are obtained by concatenating the two 8-bit duty registers
and period registers, respectively. Writing to these registers takes twice as many write cycles as for
the 8-bit PWM. The 16-bit PWM circuit has secondary buffers internally, and the user should write
to these 16-bit registers using 16-bit write instructions or high byte to low byte sequential write
instructions. During the two-byte write sequence, the secondary buffer will not be loaded from the
16-bit register. The 16-bit duty and period registers can be written to at any time; the written value
will take effect from the next cycle of the PWM period.
10.2
10.3
CLOCK SELECTION
16-BIT PWM FUNCTION
PULSE WIDTH MODULATION TIMER
MOTOROLA
10-3