TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 38

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22091/TMC22191
Genlocked Mode
In Genlocked mode, the encoder receives sync signals over
the GHSYNC and GVSYNC inputs, and provides VHSYNC
and VVSYNC to the host. The 50% sync amplitude point
occurs 50 PXCK clocks after GHSYNC goes LOW, while
VHSYNC is produced at clock 13. If GHSYNC is late, the
front porch is lengthened, if is is early, front porch is
shortened. See Figure 16, Genlock Mode Timing.
Pixel Data Control
The Pixel Data Control (PDC) signal determines the active
picture area. It may be an input or an output, as determined
by the Interface Control Register bit 1.
38
COMPOSITE
COMPOSITE
VHSYNC 1
VVSYNC 1
GHSYNC
VHSYNC
for field 1
OUTPUT
OUTPUT
PXCK
PXCK
Figure 16. Genlocked Mode Timing
Figure 15. Slave Mode Timing
The position (number of PCK cycles) of the rising edge of
PDC relative to the falling edge of VHSYNC can be found
by summing SY, BU, BR, and CBP. See Figure 17.
External Pixel Data Control
When used as an input, PDC goes HIGH four PXCK cycles
before the first valid pixel of a line is presented to the PD
input port. If this signal is late (with respect to the horizontal
blanking interval programmed in the timing control regis-
ters), the Color Back Porch (CBP) will be extended. If it is
early, incoming pixel data will be ignored until the end of the
CBP.
50% Sync Amplitude
50% Sync Amplitude
PRODUCT SPECIFICATION
24356A
24355A