TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet - Page 46

• Manufacturer Part Number: TMC22191
• Description: Digital Video Encoders/Layering Engine
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22091/TMC22191
The digital interpolation filters in TMC22x91 convert the
data stream to a sample rate of twice the pixel rate. As shown
in Figures 27 and 28, the filters decrease the sin(x)/x rolloff
and the output spectrum between f
very little energy. Since there is so little signal energy in this
frequency band, the demands placed on the output recon-
struction filter are greatly reduced. The output filter needs to
be flat to f
requirements greatly simplify the design of a filter with good
phase response and low group delay distortion. A small
amount of peaking may be used to compensate residual
sin(x)/x rolloff.
Table 16. JTAG Interface Connections
46
Reg
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
28
29
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
S
/4 and have good rejection at 3f
Signal
BYPASS (TEST)
OL
CVBS
CVBS
CVBS
CVBS
OL
OL
OL
OL
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
4
3
2
1
0
23
22
21
20
19
18
17
16
15
14
(TEST)
(TEST)
(TEST)
(TEST)
(TEST)
7
6
5
4
S
/4 and 3f
S
Reg
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
/4. The relaxed
S
/4 contains
Pin
62
63
66
67
68
69
70
71
72
73
74
75
76
77
78
79
82
83
84
1
Signal
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
LDV
PXCK
GVSYNC
GHSYNC
CVBS
CVBS
13
12
11
10
9
8
7
6
5
4
3
2
1
0
JTAG Test Interface
The JTAG test port accesses registers at every digital I/O pin
except the JTAG test port pins. Table 16 shows the sequence
of the test registers. The register number (Reg) indicates the
order in which the register data is loaded and read (Reg 1 is
loaded and read first, therefore it is at the end of the serial
path). The scan path is 59 registers long. The six TEST pins
of the TMC22091 function as JTAG registers.
The JTAG port is a 4-line interface, following IEEE Std.
1149.1-1990 specifications. The Test Data Input (TDI) and
Test Mode Select (TMS) inputs are referred to the rising
edge of the Test ClocK (TCK) input. The Test Data Output
(TDO) is referred to the falling edge of TCK.
3
2
Reg
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Pin
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
PRODUCT SPECIFICATION
Signal
CVBS
CVBS
KEY
RESET
CS
R/W
A
A
PDC
VHSYNC
VVSYNC
D
D
D
D
D
D
D
D
1
0
7
6
5
4
3
2
1
0
1
0