MC33991DW FREESCALE [Freescale Semiconductor, Inc], MC33991DW Datasheet - Page 18

• Manufacturer Part Number: MC33991DW
• Description: Gauge Driver Integrated Circuit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 15. Status Output Register
Table 13. RTZCR Full Step Time
Table 14. RTZCR Accumulator Offset
SO COMMUNICATION
register is loaded into the output register and the fault data is
clocked out MSB (OD15) first. Following a CS transition 0 to
1, the device determines if the message shift was of a valid
length and if so, latches the data into the appropriate
registers. A valid message length is one that is greater than
0 bits and a multiple of 16 bits. At this time, the SO pin is tri-
stated and the Fault
RTZ accumulator as determined by the status of bits RZ2 and
RZ3 of the RTZR, defined in Table 8. These bits represent
the integrated signal present on the non-driven coil during an
RTZ event. These bits will be logic[0] after power-on reset, or
after the RST pin transitions from logic [0] to [1]. After an RTZ
event, they will represent the last RTZ accumulator result
before the RTZ was stopped.
indicates the clock count calibrated to a value outside of the
expected range and given the tolerance specified by T
the SPI Interface Timing Table.
• 0 = Clock with in Specification
• 1 = Clock out of Specification
[1] on this bit indicates the V
the V
18
33991
TIMING DESCRIPTIONS AND DIAGRAMS
COMMUNICATION MEMORY MAPS
Read
RC12
When the CS pin is pulled low, the internal status word
These are read-only bits.
ST15:ST8— These bits represent the eight bits from the
ST7—Calibrated clock out of Spec—A logic [1] on this bit
ST6—Under voltage or over voltage Indication— A logic
0
0
0
0
0
1
“
“
“
PWRUV
RC11
ST15
OD15
0
0
0
0
0
1
“
“
“
RC3
, or it exceeded an upper limit of V
1
1
1
1
RC10
0
0
0
0
0
1
OD14
ST14
“
“
“
RC9
0
0
0
0
0
1
“
“
“
ST13
OD13
PWR
RC8
0
0
0
0
0
1
“
“
“
voltage fell to a level below
ST12
OD12
RC2
1
1
1
1
RC7
0
0
0
0
1
1
“
“
“
ST11
OD11
RC6
PWROV
0
0
1
1
0
1
“
“
“
OD10
ST10
, as
RC5
CLC
0
1
0
1
0
1
“
“
“
in
OD9
ST9
Preload Value (PV)
RC1
0
0
1
1
OD8
ST8
information. If the message length was determined to be
invalid, the status information is not cleared. It is transmitted
again during the next SPI message.
representative of the initial message bits clocked into the SI
pin. That is due to the CS pin first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
specified in the Static Electrical Characteristics Table, since
the last SPI communication. An under voltage event is just
flagged, while an over voltage event will automatically disable
the driver outputs. Because the pointer may not be in the
expected position, the master may want to re-calibrate the
pointer position with a RTZ command after the voltage
returns to a normal level. For an over voltage event, both
gauges must be re-enabled as soon as this flag returns to
logic [0]. The state machine continues to operate properly as
long as V
• 0 = Normal range
• 1 = Battery voltage fell below V
communication. A logic [1] on this bit indicates that the Gauge
1 pointer position has changed since the last SPI command.
This allows the master to confirm the pointer is moving as
commanded.
255
0
1
2
3
4
“
“
“
Status Register is now able to accept new fault status
Any bits clocked out of the SO pin after the first sixteen, is
V
ST5—Gauge 1—Movement since last SPI
PWROV
OD7
ST7
DD
is within normal range.
OD6
ST6
Initial Accumulator Value = (-16xPV)-1
RC0
OD5
ST5
0
1
0
1
Analog Integrated Circuit Device Data
OD4
ST4
PWRUV
OD3
ST3
-4081
Freescale Semiconductor
-17
-33
-49
-65
-1
“
“
“
Full Step Time (ms)
, or exceeded
OD2
ST2
49.92
54.02
58.11
62.21
ST1
OD1
OD0
ST0