LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 129

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

6.17 SMBus Controller
The LPC47S45x supports SMBus. SMBus is a serial communication protocol between a computer host and its
peripheral devices. It provides a simple, uniform and inexpensive way to connect peripheral devices to a single
computer port. A single SMBus on a host can accommodate up to 125 peripheral devices.
For a description of the SMBus protocol, please refer to the System Management Bus Specification Revision 1.0,
February 15, 1995, available from Intel Corporation.
The LPC47S45x is equipped with two independent SMBus devices, each with its own slave address, that share the
SCLK and SDAT pins. The device described in this section is a master/slave controller and is referred to in this
document as the SMBus. The second device, referred to as SMBus2, is a slave only device used to access internal
SMBus2 Registers and the I/O devices on the X-Bus. The SMBus2 device is described in a later section.
The SMBus can assert both an nIO_PME and an nIO_SMI event when enabled and following an SMBus interrupt.
Refer to registers PME_STS6, PME_EN6, SMI_STS2 and SMI_EN2 in the Runtime Registers section for more
information.
The SMBus implementation in the LPC47S45x has the following addtions over theAccess.bus:
6.17.1 CONFIGURATION REGISTERS
See the configuration registers section for the SMBus Configuration Registers (Logical Device 0x0B).
6.17.2 RUNTIME REGISTERS
Overview
The SMBus contains five registers:
The five SMBus registers occupy four addresses in the Host I/O space (Table 62).
The Own Address register and the Clock register are used to initialize the SMBus controller. Normally these registers
are written once following device reset.
The other registers are used during actual data transmission/reception. The Data register performs all serial-to-
parallel interfacing. The Control/Status register contains status information required for bus access and/or
monitoring.
Descriptions of these registers follow in the sections below.
SMSC LPC47S45x
1.
2.
1.
2.
3.
4.
5.
Added Timeout Error (TE) Bit, in D6 of the SMBus Status Register.
Added Timeout Interrupt Enable Bit D4 in the SMBus Control register.
Control
Status
Own Address
Data
Clock
Control
Status
Own Address
Data
Clock
REGISTER NAME
Table 62 − SMBus Runtime Registers
SMBus Base Address
SMBus Base Address
SMBus Base Address + 1
SMBus Base Address + 2
SMBus Base Address + 3
DATASHEET
HOST INDEX
Page 129 of 259
ISA HOST INTERFACE
HOST TYPE
R/W
R/W
R/W
W
R
Rev. 06-01-06