LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 149

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

Note : SCI events are those illustrated in the diagram as the PM1 and GPE1 registers.
Notice in the diagram above that any event enabled in the PM1 or GPE registers will always generate a signal to
initiate the wakeup logic to the power supply (i.e. activate nPS_ON). In addition, the SCI registers are able to
generate a PME or an SMI if enabled. The following is a list of options for generating PMEs and SMIs.
1.
2.
3.
SMSC LPC47S45x
PME status and enable registers. (asserts IO_PME# only)
-
SMI status and enable registers. (asserts IO_SMI# only)
-
PM1 and GPE status and enable registers (ACPI Specific Registers)
-
-
Other Wakeup Events:
•AL_REM_EN
•VTR_POR if VTR_POR_EN bit is set
•VTR POR if the nPS_ON pin was active low prior to the loss of VTR
and neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is set
To generate a PME, enable individual PME events in the PME_ENx registers and enable the PME_EN
register. The PME_EN register enables the chip to assert the IO_PME# signal.
To generate an SMI, enable individual SMI events in the SMI_ENx registers and enable Bit[7] EN_SMI in the
SMI_EN2 register at offset 17h. The EN_SMI bit enables the chip to assert the IO_SMI# signal.
Note: SMI can be routed to the Serial IRQ by setting Bit[6] of the SMI_EN2 register.
(SCI event = Assert IO_PME# and wake the system)
To generate an SCI event, enable individual events in the PM1 and GPE registers and enable the SCI_EN
bit in the PM1_CNTRL1 register at offset 60h in the Runtime Register block. The SCI_EN bit enables these
events to assert the IO_PME# signal.
Note: If the ALL_PME_EN bit is set, then all enabled PME events will generate an IO_PME# and wake the
system regardless of the PME_EN register.
(assert IO_SMI# and wake the system)
To generate an SMI event through the SCI registers, enable individual events in the PM1 and GPE registers,
set the SCI_EN bit to ‘0’, set the SMI_SCI_ENB bit to ‘0’ found in the PS_CNTRL register, and set the
EN_SMI bit to ‘1’ in the SMI_EN2 registers at offset 17h.
.
.
.
PME Events
PME_STSx,
PME_ENx
Registers
ALL 42x
+
These events are blocked from waking the
system if the PWRBTNOR_STS bit is set.
GP50/nRI2
ALL_PME
PWRBTN
SPEKEY
MDAT
KDAT
GP23
GP34
GP35
GP57
RTC
nRI1
GPE1_STS2 Reg GPE1_EN2 Reg
PM1_STS2 Reg
GPE1_STS1 Reg GPE1_EN1 Reg
.
.
.
.
.
.
FIGURE 12 − WAKEUP LOGIC
DATASHEET
PM11_EN2 Reg
Page 149 of 259
.
.
.
+
Note: the PWRBTN is always enabled for
SCI_EN
PME_STS
SMI_SCI_ENB
PME_EN
SLP_CTRL
SLP_EN
(Power Supply Control)
To Wakeup Logic
Note: SLP_CTRL=1
disables sleep
when the SLP_EN
bit is written to ‘1’.
wakeup
SMI#
IO_PME#
Rev. 06-01-06