LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 250

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

11.9.4 TIMING FOR SMBUS INITIATED I/O CYCLES WITH THE X-BUS
Note : These min/max values satisfy X-Bus write timing and the supported LCD controllers.
Note : For the complete SMBus Read/Write protocols see the section on SMBus2 or the SMBus Specification.
Note 1 : For LCD controllers the total minimum cycle time for LCDCS between latches is 1000ns. The LCDCS
latches the data when it transitions from a high to a low level. This should be easily satisfied since the SMBus
operates in the micro second range.
Note 2 : For LCD controllers A0 is the Read/nWrite control bit and A1 is the Data/Control bit. These two bits are the
LSB in the command byte.
Note 3 : The SMBus needs a minimum of 90 μ sec to deliver the Data after the Address is received. The X-Bus needs
a minimum of 400nsec to setup the address and control signals before the Data is received. To prevent the SMBus
from monopolizing the X-Bus, the chip select and control signals should be made active when both the Address and
Data byte are received on the SMBus. (The X-Bus should not begin its cycle for more than a maximum of 1 μ sec
before the Data is completely received on the SMBus)
Note 4 : The default for the Read/Write Enable Pulse Width is 540ns.
Note 5 : The LCDCS signal will be generated a minimum of 40nsec after nXRD or nXWR transitions to a low state
(i.e., LCDCS = nXWR + nXRD with a delay of 40nsec). The Pulse Width of the LCDCS signal will be 40nsec less
SMSC LPC47S45x
XAD0 - XAD7
nCS[0, 2, 3]
SMB Data
XA[0:3]
LCDCS
nWr
CS1
SYMBOL
t1
t2
t3
t4
t5
t6
-
-
FIGURE 42 − SMBUS TO X-BUS WRITE CYCLE TIMING FOR LCD AND I/O CYCLES
Command Code
SMB frequency
SMB Bit Rate
Address Setup Time
Address Hold Time
Enable Pulse Width
(See Note 4)
Data valid to nXWr active
Data Hold Time
LCDCS Address Setup Time
(See Note 5)
A
PARAMETER
DATASHEET
Data Received
Data Byte
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A
A: 180
B: 300
C: 420
D: 540
MIN
t
100
140
1
10
10
40
22
30
t
6
Address/Command
t
4
P
*Note: Timing Diagram is not to scale.
Valid Data
Address
Data
TYP
S
t
3
-
-
-
-
-
-
-
-
Slave Address
t
5
t
t
C: 455
D: 575
A: 215
B: 335
2
2
MAX
100
100
190
190
-
-
UNIT
μ sec
kHz
Rev. 06-01-06
ns
ns
ns
ns
ns
ns