UJA1079 NXP [NXP Semiconductors], UJA1079 Datasheet
UJA1079
Related parts for UJA1079
UJA1079 Summary of contents
Page 1
... Advanced low-power concept • Safe and controlled system start-up behavior • Detailed status reporting on system and sub-system levels The UJA1079 is designed to be used in combination with a microcontroller. The SBC ensures that the microcontroller always starts controlled manner. Product data sheet ...
Page 2
... Safe and predictable behavior under all conditions Programmable watchdog with independent clock source UJA1079_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
Page 3
... Name UJA1079TW/5V0/WD HTSSOP32 UJA1079TW/3V3/WD UJA1079TW/5V0 UJA1079TW/3V3 [1] UJA1079TW/5V0xx versions contain regulator (V1); UJA1079TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. UJA1079_2 Product data sheet voltages down to 4.5 V (e.g. during cranking), in accordance with BAT Description plastic thermal enhanced thin shrink small outline package; ...
Page 4
... Product data sheet SYSTEM CONTROLLER BAT BAT LIN All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip UJA1079 V1 VEXCTRL EXT. PNP CTRL VEXCC WBIAS INTN RSTN OSC TEMP LIMP 015aaa123 © NXP B.V. 2010. All rights reserved. ...
Page 5
... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 LIN core system basis chip 32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 i.c. 26 DLIN 25 LIN UJA1079 24 i.c. 23 GND 22 i.c. 21 i.c. 20 i.c. 19 WAKE2 18 WAKE1 17 LIMP 015aaa124 UJA1079 © NXP B.V. 2010. All rights reserved ...
Page 6
... IC and can be left floating, or can be connected to GND. 6. Functional description The UJA1079 combines the functionality of a LIN transceiver, a voltage regulator and a watchdog (UJA1079/xx/WD versions single, dedicated chip. It handles the power-up and power-down functionality of the ECU and ensures advanced system reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation of external switches ...
Page 7
... UJA1079_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Figure 3. These modes are discussed in © NXP B.V. 2010. All rights reserved ...
Page 8
... V below BAT power-on threshold V th(det)pon LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1079 system controller UJA1079_2 Product data sheet Overtemp V1: OFF limp home = LOW (active) LIN: Off and high resistance watchdog: OFF Off V1: OFF LIN: Off and high resistance ...
Page 9
... Rev. 02 — 27 May 2010 LIN core system basis chip ). In Off mode, the voltage regulator is disabled and Table 11). Table 6) with bus wake-up detection enabled or Section 6.7.1. The watchdog can be 6.1.3; the SBC will enter Standby mode) UJA1079 ), th(det)pon ) th(det)pon (Table 4). , causing the th(act)otp , causing the th(act)otp © ...
Page 10
... The watchdog is off and the reset pin is Section Section 6.5.1 and Table Figure 4). All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip 6.5.1) system reset. The value of the mode 11). © NXP B.V. 2010. All rights reserved. . th(act)otp , w(rst) ...
Page 11
... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 LIN core system basis chip LSB 12 01 LSB Read/Write access bits 11... 0 WD_and_Status register Mode_Control register Int_Control register Int_Status register UJA1079 X floating mce634 © NXP B.V. 2010. All rights reserved ...
Page 12
... WAKE1 input voltage below switching threshold (V 1: WAKE1 input voltage above switching threshold (V wake-up 2 status 0: WAKE2 input voltage below switching threshold (V 1: WAKE2 input voltage above switching threshold (V All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip ) th(sw) ) th(sw) ) ...
Page 13
... V1 threshold current for activating the external PNP transistor; load current rising mA; V1 threshold current for deactivating the external th(act)PNP PNP transistor; load current falling; I All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip = 50 mA; see Figure 7 th(deact)PNP = 15 mA; see Figure 7 th(deact)PNP © ...
Page 14
... WAKE1 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip . BAT © NXP B.V. 2010. All rights reserved ...
Page 15
... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
Page 16
... The on-chip oscillator is supplied by an internal supply that is connected to V and is independent of V1. BAT 6.4 Watchdog (UJA1079/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms. ...
Page 17
... SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor on RSTN pin) A watchdog overflow in Timeout mode requests a cyclic interrupt (CI not already pending. The UJA1079 provides three signals for dealing with reset events: • RSTN input/output for performing a global ECU system reset or forcing an external reset • ...
Page 18
... Rev. 02 — 27 May 2010 LIN core system basis chip Section 6.6. the SBC leaving Off ) modes. A short reset pulse is th(rel)otp Table 11). 5) via the SPI interface. Pin EN will be HIGH when NORMAL UJA1079 by fltr STANDBY 015aaa074 © NXP B.V. 2010. All rights reserved ...
Page 19
... Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional transceivers supplied by pin BAT and delivers up to 250 (depending on the UJA1079 version). To prevent the device overheating at high ambient temperatures or high average currents, an external PNP transistor can be connected as illustrated in configuration, the power dissipation is distributed between the SBC and the PNP transistor ...
Page 20
... V1 −165 mA 165 mA PNP current V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip 215 th(deact)PNP (PDC = 0) 015aaa111 015aaa075 © ...
Page 21
... The status of V1 can be read via bit V1S in the WD_and_Status register 6.7 LIN transceiver The analog section of the UJA1079 LIN transceiver is identical to that integrated into the TJA1021. The transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN ...
Page 22
... The LIN transceiver can be woken up remotely via pin LIN in wake(busdom)min ), the transmitter is disabled, driving the bus lines to a recessive to(dom)TXDL Table All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip (see Table 11). to guarantee safe, defined states ...
Page 23
... UJA1079 BAT 47 kΩ 47 kΩ WBIAS WAKE1 WAKE2 GND All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip disable bias disable bias wake level latched PDTA144E biasing of switches sample of sample of WAKEx WAKEx © ...
Page 24
... Clearing bit LWI in Standby mode only clears the Section 6.1.6 “Overtemp All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip mode”). When the temperature falls © NXP B.V. 2010. All rights reserved ...
Page 25
... TEST2; referenced to other reference pins any other pin MM any pin CDM corner pins any other pin All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Min Max Unit −0 −0 ...
Page 26
... Product data sheet Conditions . The rating for T limits the allowable combinations of power dissipation (P) and ambient vj vj All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Min Max Unit −40 °C +125 + P × R ...
Page 27
... Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm × will reduce thermal resistance (see All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip optional heatsink top layer optional heatsink top layer ...
Page 28
... Parameter thermal resistance from junction to ambient All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 LIN core system basis chip PCB Cu heatsink area (cm Conditions single-layer board four-layer board UJA1079 015aaa138 Typ Unit [1] 78 K/W [2] 39 K/W © NXP B.V. 2010. All rights reserved. ...
Page 29
... V BAT LIN Active mode (dominant) STBCL = TXDL DLIN LIN BAT All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Min Typ Max 4 ...
Page 30
... LIN = 5. 3.234 3.3 ≥ 560 pF LIN = 4 3.201 3.3 ≥ 220 pF LIN = 4 2.97 3 4.5 - 2.97 - 3.5 - 4.56 - 3.025 - −600 - UJA1079 Max Unit - mV 5.3 V 5.5 V 300 mV 7.5 V 5.1 V 5.15 V 5.1 V 5.1 V 5.1 V 3.366 V 3.399 V 3.366 V Ω 3 4.75 V 3.135 V 3. ...
Page 31
... Section 6.6 240 - < BAT 0. 100 - 50 130 50 130 −5 - − 0.4 V −30 - 1.6 - − UJA1079 Max Unit 191 114 120 330 mV 0. 900 mV 400 kΩ 400 kΩ μA +5 −1.6 ...
Page 32
... V BAT 100 - 1.6 - − 100 - 100 - − wake 0 0. 100 - UJA1079 Max Unit −100 μ μA 540 0. 0 0.3 0. 900 −1 0 900 mV 20 kΩ 3.75 V 1000 mV μA 0 μ ...
Page 33
... V )/2 0.475 th(dom)RX × BAT BAT 0.05 × 0.15 × th(dom) BAT BAT - - = 0.4 0.65 165 180 126 138 UJA1079 Max Unit 25 kΩ −1 kΩ 100 mA μA 2 μA +10 μA 10 μ 0.4V V BAT 0.525 × BAT 0.175 × ...
Page 34
... LSC = 0 BAT V = 0.76V th(rec)RX(max) BAT V = 0.593V th(dom)RX(max) BAT LSC = 0 BAT All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Min Typ Max 140 320 - - 110 ...
Page 35
... Window mode only Normal, Standby and Sleep modes watchdog Window mode only = 660 Ω kΩ 6.8 nF and All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Min Typ [ BAT = 50 μs [3] t BAT ...
Page 36
... PD(RX)f PD(RX)r t PD(RX)r All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip after the start of the watchdog trig(wd)1 Table , but not more than t , after the start of the trig(wd)1 trig(wd)2 BAT ...
Page 37
... Product data sheet T cy(clk clk(H) clk( su(D) h(D) MSB X MSB All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip t t SPILAG WH(S) LSB X t v(Q) floating LSB 015aaa045 © NXP B.V. 2010. All rights reserved ...
Page 38
... Rev. 02 — 27 May 2010 LIN core system basis chip detail 8.3 0.75 0.65 1 0.2 0.1 7.9 0.50 EUROPEAN PROJECTION UJA1079 SOT549 θ θ 0.78 8 0.1 o 0.48 0 ISSUE DATE 03-04-07 05-11-02 © NXP B.V. 2010. All rights reserved ...
Page 39
... Solder bath specifications, including temperature and impurities UJA1079_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
Page 40
... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 17. All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip Figure 17) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
Page 41
... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved. ...
Page 42
... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 LIN core system basis chip Change notice Supersedes - UJA1079_1 , I ESD R(V1-BAT and V th(cntr)RX th(hys)RX for RSTN pin det(CL)L wake(busdom)min - - UJA1079 for RSTN pin, OL © NXP B.V. 2010. All rights reserved ...
Page 43
... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
Page 44
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1079 LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
Page 45
... Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 Introduction 6.2.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.3 WD_and_Status register 6.2.4 Mode_Control register . . . . . . . . . . . . . . . . . . 13 6.2.5 Int_Control register . . . . . . . . . . . . . . . . . . . . . 14 6.2.6 Int_Status register 6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Watchdog (UJA1079/xx/WD versions 6.4.1 Watchdog Window behavior . . . . . . . . . . . . . . 16 6.4.2 Watchdog Timeout behavior . . . . . . . . . . . . . . 17 6.4.3 Watchdog Off behavior . . . . . . . . . . . . . . . . . . 17 6.5 System reset 6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.3 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6.1 Battery pin (BAT ...