ADM706R AD [Analog Devices], ADM706R Datasheet - Page 5

• Manufacturer Part Number: ADM706R
• Description: +3 V, Voltage Monitoring uP Supervisory Circuits
• Manufacturer: AD [Analog Devices]

REV. A
CIRCUIT INFORMATION
Power Fail Reset
The reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the V
the reset threshold. The actual reset threshold voltage is depen-
dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage
on V
reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power-
up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the
supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad-
ditional 200 ms.
The reset output is guaranteed to remain valid with V
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high reset (RESET) signal;
the ADM706R/S/T provides an active low (RESET) signal;
while the ADM708R/S/T provides both RESET and RESET.
POWER FAIL
POWER FAIL
WATCHDOG
INPUT (WDI)
INPUT (PFI)
INPUT (PFI)
CC
V
V
Figure 1. ADM706 Functional Block Diagram
Figure 2. ADM708 Functional Block Diagram
rises above the threshold. This is intended as a power-on
MR
MR
CC
CC
*
*
VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
V
V
1.25V
1.25V
REF
REF
WATCHDOG
TRANSITION
DETECTOR
V
V
*
CC
*
CC
70 A
70 A
GENERATOR
WATCHDOG
WATCHDOG
TIMEBASE
GENERATOR
RESET &
RESET
TIMER
RESET
ADM708
ADM706
CC
input is below
WATCHDOG
OUTPUT(WDO)
RESET,
(P = RESET)
POWER FAIL
OUTPUT (PFO)
RESET
POWER FAIL
OUTPUT (PFO)
RESET
CC
as low
–5–
Manual Reset
The manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.
Watchdog Timer (ADM706)
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in
an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in-
terrupt service routine should then be used to rectify the
problem.
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.
When V
whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/
RESET going active.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when V
the reset threshold.
RESET
WDO
RESET
V
MR
WDO
CC
WDI
t
WP
CC
Figure 3. RESET , MR and WDO Timing
ADM706P/R/S/T, ADM708R/S/T
falls below the reset threshold, WDO is forced low
VRT
NOTE: RESET = COMPLEMENT OF RESET
Figure 4. Watchdog Timing
t
WD
VRT
RESET EXTERNALLY
TRIGGERED BY MR
t
RS
t
WD
CC
MR EXTERNALLY
DRIVEN LOW
t
RS
falls below
t
RS
t
WD