ADM706R AD [Analog Devices], ADM706R Datasheet - Page 8

• Manufacturer Part Number: ADM706R
• Description: +3 V, Voltage Monitoring uP Supervisory Circuits
• Manufacturer: AD [Analog Devices]

Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, then WDO goes
low and a nonmaskable interrupt is generated. This interrupt
routine may be used to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, then the WDO output should be connected to the
input as shown in Figure 16.
Monitoring Additional Supply Levels
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors
R1 and R2 are selected such that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The PFO output
may be connected to the MR input so that a RESET is gener-
ated when the supply drops out of tolerance. In this case if
either supply drops out of tolerance, a RESET will be generated.
ADM706P/R/S/T, ADM708R/S/T
0.160 (4.06)
0.115 (2.93)
(5.33)
0.210
MAX
PIN 1
0.022 (0.558)
0.014 (0.356)
MR
PFI
Figure 16. RESET from WDO
8
0.430 (10.92)
0.348 (8.84)
0.100 (2.54)
1
ADM706
BSC
GND
0.070 (1.77)
0.045 (1.15)
8-Lead Plastic DIP
RESET
WDO
WDI
5
4
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
(N-8)
SEATING
PLANE
0.130
(3.30)
MIN
0.325 (8.25)
0.300 (7.62)
RESET
I/O LINE
0.015 (0.381)
0.008 (0.204)
P
0.195 (4.95)
0.115 (2.93)
Dimensions shown in inches and (mm).
OUTLINE DIMENSIONS
–8–
In order to prevent contention for microprocessors with a bidi-
rectional reset line, a current limiting resistor should be inserted
between the ADM70x RESET output pin and the P reset pin.
This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 k . If the re-
set output is required for other uses, then it should be buffered
as shown in Figure 18.
Ps with Bidirectional RESET
Figure 17. Monitoring 3 V/3.3 V and an Additional
Supply, V
0.0098 (0.25)
0.0040 (0.10)
0.1574 (4.00)
0.1497 (3.80)
R2
R1
PIN 1
SEATING
V
PLANE
X
Figure 18. Bidirectional I-O RESET
ADM70x
X
+3V/+3.3V
GND
V
0.1968 (5.00)
0.1890 (4.80)
0.0500 (1.27)
8
1
CC
RESET
+3V/+3.3V
BSC
PFI
MR
0.0192 (0.49)
0.0138 (0.35)
ADM706
V
CC
GND
5
4
8-Lead SOIC
0.2440 (6.20)
0.2284 (5.80)
RESET
0.0688 (1.75)
0.0532 (1.35)
WDI
PFO
(SO-8)
RESET
0.0098 (0.25)
0.0075 (0.19)
GND
P
RESET
BUFFERED
RESET
8
0
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
0.0160 (0.41)
P
REV. A
45