ISL6313 INTERSIL [Intersil Corporation], ISL6313 Datasheet - Page 12

• Manufacturer Part Number: ISL6313
• Description: Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

voltage on the APA pin and comparing it to a filtered copy of
the voltage on the COMP pin. The voltage on the APA pin is
a copy of the COMP pin voltage that has been negatively
offset. If the APA pin exceeds the filtered COMP pin voltage
an APA event occurs and all of the channels are forced on.
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pin must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, R
connects from the APA pin to the COMP pin. A 100μA
current flows across R
trip level as described in Equation 3 below. An APA trip level
of 500mV is recommended for most applications. A 1000pF
capacitor, C
resistor to help with noise immunity.
Number of Active Channels
The default number of active channels on the ISL6313 is two
for 2-phase operation. If single phase operation is desired
the ISEN2- pin should be tied to the VCC pin. This will
disable Channel 2, so only Channel 1 will fire. In single
phase operation all of the Channel 2 pins should be left
unconnected including the PHASE2, LGATE2, UGATE2,
BOOT2, and ISEN2+ pins.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sensed
continuously every switching cycle. The sensed currents, I
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I
load-current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sensed current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 4, with error
correction for channel 1 represented. In the figure, the cycle
average current, I
sensed current, I
V
APA TRIP
(
)
APA
=
R
, should also be placed across the R
APA
1
AVG
AVG
, to create an error signal I
⋅
100
, provides a measure of the total
, is compared with the channel 1
APA
×
into the APA pin to set the APA
10
12
–
6
ER
APA
.
, that
APA
(EQ. 3)
n
,
ISL6313
ISL6313
The filtered error signal modifies the pulse width
commanded by V
I
correction is applied to each active channel.
Continuous Current Sensing
In order to realize proper current-balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I
scaled version of the inductor current.
The ISL6313 supports inductor DCR current sensing to
continuously sense each channel’s current for
channel-current balance. The internal circuitry, shown in
Figure 6 represents channel n of an N-channel converter.
This circuitry is repeated for each channel in the converter,
but may not be active depending on how many channels are
operating.
ER
V
COMP
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT-
toward zero. The same method for error signal
FILTER
FIGURE 5. CONTINUOUS CURRENT SAMPLING
+
I
ER
BALANCE ADJUSTMENT
-
+
f(s)
∑
∑
I
1
COMP
L
-
. This sensed current, I
I
AVG
PWM
MODULATOR
WAVEFORM
to correct any unbalance and force
SWITCHING PERIOD
÷ 2
RAMP
TIME
I
I
SEN
L
+
∑
+
-
+
PWM1
SEN
, is simply a
I
2
March 5, 2007
CONTROL
TO GATE
LOGIC
FN6448.0