AMIS30421C4211G ONSEMI [ON Semiconductor], AMIS30421C4211G Datasheet - Page 32

• Manufacturer Part Number: AMIS30421C4211G
• Description: Micro-Stepping Stepper Motor Bridge Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Remark: Bit 3 and bit 5 of Control Register 1 should always be ‘0’ (zero)!
Control Register 2 (CR2)
mode. It also has some parameters that can be used to set the SLA.
Table 14. CONTROL REGISTER 1 PARAMETERS
Table 15. CONTROL REGISTER 2
Table 16. CONTROL REGISTER 2 PARAMETERS
Control Register 2 is located at address 0x03 and can be used to enable the motor driver and to put the motor driver in sleep
Address
NO_CROSS[1:0]
0x03
Parameter
Parameter
SLAG[2:0]
DIRCTRL
MOTEN
IO_OT
PWMJ
NXTP
SLAT
SLP
Access
Reset
Data
Value
Value
000
001
010
100
101
011
110
111
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MOTEN
Bit 7
R/W
0
Not Transparent
Negative Edge
Normal Mode
Positive Edge
Sleep Mode
Transparent
Open Drain
Push Pull
Disabled
Disabled
Enabled
Enabled
1000 ns
0.0625
0.0625
0.0625
0.0625
250 ns
500 ns
Value
0.125
Value
CCW
0.25
Bit 6
0 ns
CW
R/W
SLP
0.5
1
0
Control Register 2 (CR2)
http://onsemi.com
Bit 5
R/W
0
−
Enables the PWM regulator.
Remark: the regulator is automatically disabled if one of the
bits in Status Register 1 or 2 is set.
Enables the sleep mode (power down mode)
Defines the type of SLA sampling.
Defines the motor terminal voltage division factor for the
SLA−pin.
Defines the direction of rotation.
Remark: CW and CCW is relative. Direction of rotation will
be defined by the status of the DIR−pin and connection of
the stepper motor!
Defines the active edge on the NXT−pin.
Defines the output type of WDb−, ERRb− and DO−pin
Enables or disables PWM jitter
Defines the time between switching off one MOSFET and
switching on the other MOSFET of the same half H−bridge
(= t
nocross
32
SLAT
Bit 4
R/W
).
0
Bit 3
R/W
Description
Description
0
SLAG[2:0]
Bit 2
R/W
0
Bit 1
R/W
0
SLA_OFFS
Bit 0
R/W
0
Info
Info
p19
p19
p24
p15
p13
p19
p22
p20
p20