MD56V62160E-10 OKI [OKI electronic componets], MD56V62160E-10 Datasheet
MD56V62160E-10
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MD56V62160E-10 Summary of contents
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... Burst Length ( Full Page) - Data scramble (sequential, interleave) CBR auto-refresh, Self-refresh capability • • Packages: 54-pin 400 mil plastic TSOP (TypeII) PRODUCT FAMILY Family Frequency MD56V62160E-7 MD56V62160E-10 1,048,576-word 16-bit Synchronous dynamic RAM fabricated in TSOP(2)54-P-400-0.80-K ( Access Time (Max.) Max. t AC2 143 MHz ...
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... 54-Pin Plastic TSOP(II) (K Type) Pin Name UDQM, LDQM DQi pin and V SS FEDD56V62160E-01 MD56V62160E DQ16 DQ15 50 DQ14 DQ13 47 DQ12 DQ11 44 DQ10 43 ...
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... Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H” LDQM edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. DQi Data inputs/outputs are multiplexed on the same pin. : RA0 – RA11 : CA0 – CA7 FEDD56V62160E-01 MD56V62160E 3/34 ...
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... Decoders Column 8 Decoders Sense Amplifiers Row Word 16Mb 12 Decoders Drivers Memory Cells Row Word 16Mb 12 Decoders Drivers Memory Cells Sense Amplifiers Column 8 8 Decoders FEDD56V62160E-01 MD56V62160E I/O Controller Input Input Data Buffers Register 16 16 DQ1 - DQ16 Read Output Data Buffers Register 4/34 ...
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... opr *: Symbol Min 3 2 0.3 IL Symbol C CLK OUT FEDD56V62160E-01 MD56V62160E Value Unit –0 0 –0.5 to 4.6 V –55 to 150 °C 1000 °C (Voltages referenced Typ. Max. Unit 3 ...
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... Min CKE Min CKE Min Min. CC CKE Min. RC CKE Min CKE Min FEDD56V62160E-01 MD56V62160E E-10 Unit Note Max. Min. Max. 2.4 V 0.4 0 1,2 135 115 mA 1 ...
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... Notes: A7, A8, A10, A11, A12 and A13 should stay “L” during mode set cycle. MD56V62160E supports two methods of Power on Sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the V voltage has reached the specified level, pause for 200 s or more with the input kept in CC NOP state ...
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... RAS t 20 RCD RRD t 64 REF t t +1CLK t RDE CCD l 1 CKE l 2 DOZ l 0 DOD FEDD56V62160E-01 MD56V62160E Note1, 2 E-10 Unit Note Min. Max ...
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... V T MD56V62160 E-7 Symbol Min. Max DWD l CL ROH l 2 MRD l 2 OWD = FEDD56V62160E-01 MD56V62160E Note1, 2 E-10 Unit Note Min. Max. 0 Cycle CL Cycle 2 Cycle 2 Cycle 50 pF (External Load) and 9/34 ...
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... UDQM, LDQM Row Active Read Command 2, Burst Length Qa0 Qa1 Qa2 Qa3 t OH Row Active Precharge Command Write Command FEDD56V62160E-01 MD56V62160E Cb0 Db0 Db1 Db2 Db3 Precharge Command 10/34 ...
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... OLZ UDQM, LDQM Row Active Write Command Read Command 2, Burst Length = High CCD OHZ OWD t SI Precharge Command Read Command FEDD56V62160E-01 MD56V62160E 11/34 ...
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... After the end of burst, bank D holds the idle status. 1 After the end of burst, bank D is precharged automatically. A13 Operation 0 Bank A is precharged. 1 Bank B is precharged. 0 Bank C is precharged. 1 Bank D is precharged. X All banks are precharged. ) after UDQM, LDQM entry. OHZ FEDD56V62160E-01 MD56V62160E 12/34 ...
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... Input data during the precharge input cycle will be masked internally. 2, Burst Length = High Cc0 Cd0 Dc0 Dc1 Dd0 l t OWD WR Note 1 Write Command Precharge Command Write Command after the last write data input. WR FEDD56V62160E-01 MD56V62160E Note 2 13/34 ...
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... If you set A9 to high during mode register set cycle, the write burst length is set Burst Length = Cb0 Note 1 Qa0 Qa1 Qa2 Qa3 Db0 t OH Write Command Read Command FEDD56V62160E-01 MD56V62160E Cc0 BS Qc0 Qc1 Qc2 Qc3 Precharge Command 14/34 ...
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... Qa1 Qa2 Qa3 A-Bank Precharge Start Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start B Bank Write with Auto Precharge Auto Precharge FEDD56V62160E-01 MD56V62160E Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 ...
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... Read Command (A-Bank High RBb CBb RAc RBb RAc QBb1 QBb2 QBb3 QBb4 Read Command (B-Bank) Row Active Precharge Command (A-Bank) Precharge Command (A-Bank) FEDD56V62160E-01 MD56V62160E CAc QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) (B-Bank) 16/34 ...
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... Write Command (A-Bank High CBb RAc RAc DBb0 DBb1 DBb2 DBb3 Precharge Command (A-Bank) Precharge Command Write Command Row Active (B-Bank) (A-Bank) FEDD56V62160E-01 MD56V62160E CAc DAc0 DAc1 Write Command (A-Bank) Precharge Command (A-Bank) (B-Bank) 17/34 ...
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... CS is ignored when RAS, CAS and WE are high at the same cycle High CBb CAc CBd Read Command (B-Bank) Read Command Read Command (B-Bank) (A-Bank) FEDD56V62160E-01 MD56V62160E CAe I ROH Precharge Command (A-Bank) Read Command (A-Bank) 18/34 ...
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... Row Active (A-Bank) (B-Bank) Write Command (A-Bank High CBb CAc DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 Write Command (B-Bank) Write Command Write Command (B-Bank) (A-Bank) FEDD56V62160E-01 MD56V62160E CBd Precharge Command (Both Bank) 19/34 ...
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... Row Active (A-Bank) (B-Bank) Read Command (A-Bank High RBb CBb RAc RBb RAc QBb0 QBb1 QBb2 QBb3 Write Command (B-Bank) Precharge Command Row Active (A-Bank) (A-Bank) FEDD56V62160E-01 MD56V62160E CAc QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) 20/34 ...
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... CAa0 ADDR A12, A13 A10 QAa0 QAa1 QAa2 QAa3 DQ WE UDQM, LDQM Read Command (A-Bank High CBb0 CAc0 DBb0 DBb1 DBb2 DBb3 Write Command Read Command (B-Bank) (A-Bank) FEDD56V62160E-01 MD56V62160E QAc0 QAc1 QAc2 QAc3 21/34 ...
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... When UDQM is set High, the input/output data of DQ9 – DQ16 is masked Note 1 Cb Qa2 Qb0 Qb1 t t OHZ OHZ Note 2 Read Command Read DQM Read DQM FEDD56V62160E-01 MD56V62160E Note 1 Cc Dc0 Dc2 Note 3 Write Write DQM DQM Write CLOCK Suspension Command 22/34 ...
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... In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM, LDQM must be high at least 3 clocks prior to the write command Note 1 Cb0 Da0 Db0 Db1 Db2 Db3 t WR Precharge Command Write Command FEDD56V62160E-01 MD56V62160E 23/34 ...
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... If row precharge is asserted before a burst read ends, then the read data will not output after l equals CAS latency High Note 1 Qa2 Qa3 Qa4 Qa5 l ROH Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 l ROH Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 l ROH Precharge Command FEDD56V62160E-01 MD56V62160E ROH 24/34 ...
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... Qa0 Qa1 Qa2 Qa3 Qa4 UDQM, LDQM Read Command Burst Stop Command High Cb Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Write Command FEDD56V62160E-01 MD56V62160E Burst Stop Command 25/34 ...
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... Power-down Exit *Note: 1. When both banks are in precharge state, and if CKE is set low, then the MD56V62160E enters power-down mode and maintains the mode while CKE is low release the circuit from power-down mode, CKE has to be set high for longer than t ...
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... OKI Semiconductor Self Refresh Cycle CLK CKE RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Self Refresh Entry Hi-Z Self Refresh Exit FEDD56V62160E-01 MD56V62160E Row Active 27/34 ...
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... Mode Register Set Cycle CLK High CKE CS l MRD RAS CAS ADDR Key UDQM, LDQM MRS New Command Auto Refresh Cycle High Auto Refresh FEDD56V62160E-01 MD56V62160E Auto Refresh 28/34 ...
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... BA X ILLEGAL CA, A10 ILLEGAL ILLEGAL RA, A10 ILLEGAL NOP (Continue Burst to End and enter Row Precharge NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL CA, A10 FEDD56V62160E-01 MD56V62160E Action 29/34 ...
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... A10 ILLEGAL NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL NOP = No OPeration command and t to prevent bus contention. WR FEDD56V62160E-01 MD56V62160E Action 30/34 ...
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... satisfied when CKE transition from “L” to “H”, CKE operates PDE FEDD56V62160E-01 MD56V62160E INVALID Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDD56V62160E-01 MD56V62160E (Unit: mm) Package material Epoxy resin Lead frame material ...
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... OKI Semiconductor REVISION HISTORY Document Date No. FEDD56V62160E-01 Feb. 4, 2002 Page Previous Current Edition Edition – – First edition FEDD56V62160E-01 MD56V62160E Description 33/34 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDD56V62160E-01 MD56V62160E Copyright 2001 Oki Electric Industry Co., Ltd. 34/34 ...