AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet - Page 30

• Manufacturer Part Number: AT42QT1111MU
• Manufacturer: ATMEL [ATMEL Corporation]

7.5
30
Address 1: Guard Key/Comms Options
AT42QT1111-MU/AT42QT1111-AU
REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key
acquisition. The number entered is a multiple of 16 ms. If “0” is entered, the device will operate
in a continuous “free run” mode; that is, the QT1111 will not sleep after its cycle is completed but
will begin the next key acquisition cycle immediately.
Default KEY_AC value:
Default MODE value:
Default SIGNAL value:
Default SYNC value:
Default REPEAT_TIME value:
Table 7-3.
GUARD_KEY: specifies the key (0 to 10) to be used as a guard channel (see
page
GD_EN: enables the use of a guard key; 0 = disable, 1 = enable.
SPI_EN: enables the Quick SPI interface; 0 = disable, 1 = enable (see
Table 7-4.
See
To exit this mode (and clear the “SPI_EN” bit), the command “0x36” should be sent. To save the
settings to EEPROM and make Quick SPI mode active on startup, send the “Store to EEPROM”
command (0x0A). Any other data sent is ignored in Quick SPI mode.
CHG: the CHANGE pin mode (see
CRC: enables or disables CRC; 0 = disable, 1 = enable. When this option is enabled, each data
exchange must have a CRC byte appended.
When report or setup data is being returned by the QT1111, a 1-byte checksum is returned. The
host should confirm that this checksum is correct and, if not, should request the report again.
Address
Byte
Section 4.1.6 on page 16
1
0
1
2
3
4
5
6
7) .
0 = “Data” mode. In this mode the “Change” pin is asserted to indicate unread data.
1 = “Touch” mode. In this mode the “Change” pin is asserted when a key is being touched
or is in detect.
Bit 7
Bit 7
Guard Key/Comms Options
Status Information Bytes
Key 3 status
Key 7 status
Key 3 error
Key 7 error
Reserved
Reserved
Bit 6
Bit 6
GUARD_KEY
for details of the Quick SPI Mode report.
Bit 5
Bit 5
Section 4.5 on page
Key 10 status
Key 2 status
Key 6 status
Key 10 error
Key 2 error
Key 6 error
1 (timed)
0 (7-key mode)
1 (parallel)
1 (edge)
2 (32 ms cycle)
Bit 4
Bit 4
Counter
GD_EN
17):
Bit 3
Bit 3
Key 1 status
Key 5 status
Key 9 status
Key 1 error
Key 5 error
Key 9 error
SPI_EN
Bit 2
Bit 2
Table
7-4).
Bit 1
CHG
Bit 1
Key 0 status
Key 4 status
Key 8 status
Section 2.3 on
Key 0 error
Key 4 error
Key 8 error
9571A–AT42–02/10
Bit 0
CRC
Bit 0