AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet - Page 33

• Manufacturer Part Number: AT42QT1111MU
• Manufacturer: ATMEL [ATMEL Corporation]

7.10
7.11
7.12
9571A–AT42–02/10
Address 6: Lower Burst Limit (LBL)
Addresses 7–8: AKS Mask
Addresses 9–15: Detect0 – Detect6 PWM
Table 7-9.
Normal QTouch signals are in the range of 100 to 1000 counts for each key. The lower burst
limit determines the minimum signal that is considered as a valid acquisition. If the count is lower
than the lower burst limit, it is considered not to be valid and the key is set to an Error state.
Note:
Default value:
Table 7-10.
AKS_n (AKS Mask): 0 = key n AKS disabled, 1 = key n AKS enabled (where n is 0–10).
These bits control which keys have AKS enabled (see
corresponding key has AKS enabled; a “0” means that the corresponding key has AKS disabled.
Default AKS mask:
Each of the 7 detect pins can be configured to output a PWM signal to indicate whether the key
is touched (in detect) or not touched (out of detect).
The Detect outputs must be enabled by selecting 7-key mode in the “Device Mode” setting (see
Section 7.4 on page
individual “Detect” outputs for each key (see
Table 7-11.
IN_DETECTn: PWM to output when key n is “In Detect” (where n is 0–7).
Address
Address
Address
10
11
12
13
14
15
6
7
8
9
Where a key has a signal of less than the LBL, a detection is not reported on that key.
AKS_7
Bit 7
Bit 7
Bit 7
Lower Burst Limit
AKS Mask
Detect0 – Detect6 PWM
29), and the corresponding “Key to LED” bits must be set to enable the
AKS_6
Bit 6
Bit 6
Bit 6
IN_DETECT0
IN_DETECT1
IN_DETECT2
IN_DETECT3
IN_DETECT4
IN_DETECT5
IN_DETECT6
18
0x07 and 0xFF (all keys have AKS enabled)
AT42QT1111-MU/AT42QT1111-AU
AKS_5
Bit 5
Bit 5
Bit 5
Section 7.14 on page
AKS_4
Bit 4
Bit 4
Bit 4
LBL
AKS_3
Section 3 on page
Bit 3
Bit 3
Bit 3
AKS_10
AKS_2
35).
Bit 2
Bit 2
Bit 2
OUT_DETECT0
OUT_DETECT1
OUT_DETECT2
OUT_DETECT3
OUT_DETECT4
OUT_DETECT5
OUT_DETECT6
8). A “1” means the
AKS_9
AKS_1
Bit 1
Bit 1
Bit 1
AKS_8
AKS_0
Bit 0
Bit 0
Bit 0
33