ADUC812_03 AD [Analog Devices], ADUC812_03 Datasheet - Page 23

• Manufacturer Part Number: ADUC812_03
• Manufacturer: AD [Analog Devices]

To drive significant loads with the DAC outputs, external
buffering may be required, as illustrated in Figure 22.
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high impedance state (or
“three-state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, then a pull-down resistor must
be added to each DAC output. Assuming this resistor is in place,
REV. E
Figure 21. Source and Sink Current Capability with
V
REF
= V
3
2
1
0
0
Figure 22. Buffering the DAC Outputs
DD
= 3 V
SOURCE/SINK CURRENT – mA
5
10
9
10
ADuC812
15
–23–
the DAC outputs will remain at ground potential whenever the
DAC is disabled. However, each DAC output will still spike
briefly when power is first applied to the chip, and again when
each DAC is first enabled in software. Typical scope shots of
these spikes are given in Figure 23 and Figure 24, respectively.
Figure 23. DAC Output Spike at Chip Power-Up
Figure 24. DAC Output Spike at DAC Enable
5
200 s/DIV
s/DIV, 1V/DIV
DAC OUT – 500mV/DIV
AV
DD
ADuC812
– 2V/DIV