ADUC812_03 AD [Analog Devices], ADUC812_03 Datasheet - Page 48

• Manufacturer Part Number: ADUC812_03
• Manufacturer: AD [Analog Devices]

ADuC812
Parameter
EXTERNAL DATA MEMORY READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
RLRH
AVLL
LLAX
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
RLAZ
WHLH
RD Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
RD Low to Valid Data In
Data and Address Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
RD Low to Address Float
RD or WR High to ALE High
PORT 0 (I/O)
PORT 2 (O)
PSEN (O)
ALE (O)
RD (O)
MCLK
t
AVLL
Figure 52. External Data Memory Read Cycle
A0–A7 (OUT)
A16–A23
t
AVDV
t
LLAX
t
AVWL
t
LLWL
t
LLDV
Min
400
43
48
0
200
203
43
–48–
t
12 MHz
RLAZ
t
RLDV
Max
252
97
300
0
123
517
585
A8–A15
t
DATA (IN)
RLRH
t
RHDX
Min
6t
t
t
0
3t
4t
t
CK
CK
CK
CK
CK
CK
– 40
– 35
– 40
Variable Clock
– 100
– 50
– 130
t
WHLH
t
RHDZ
Max
5t
2t
8t
9t
3t
0
6t
CK
CK
CK
CK
CK
CK
– 70
– 150
– 165
+ 50
– 100
– 165
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. E