ADUC812_03 AD [Analog Devices], ADUC812_03 Datasheet - Page 49

• Manufacturer Part Number: ADUC812_03
• Manufacturer: AD [Analog Devices]

Parameter
EXTERNAL DATA MEMORY WRITE CYCLE
t
t
t
t
t
t
t
t
t
REV. E
WLWH
AVLL
LLAX
LLWL
AVWL
QVWX
QVWH
WHQX
WHLH
WR Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup before WR
Data and Address Hold after WR
RD or WR High to ALE High
PORT 2 (O)
PSEN (O)
ALE (O)
WR (O)
MCLK
t
AVLL
Figure 53. External Data Memory Write Cycle
A16–A23
A0–A7
t
LLAX
t
AVWL
t
LLWL
Min
400
43
48
200
203
33
433
33
43
–49–
12 MHz
t
QVWX
DATA
Max
300
123
t
t
A8–A15
WLWH
QVWH
t
t
t
Min
6t
t
t
3t
4t
7t
CK
CK
CK
CK
CK
Variable Clock
CK
CK
CK
CK
– 40
– 35
– 50
– 50
– 40
– 100
– 50
– 130
– 150
t
t
WHLH
WHQX
Max
3t
6t
CK
CK
+ 50
– 100
ADuC812
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns