AD9393/PCBZ AD [Analog Devices], AD9393/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9393/PCBZ
• Description: Low Power HDMI Display Interface
• Manufacturer: AD [Analog Devices]

AUDIO BOARD LEVEL MUTING
The audio can be muted through the infoframes or locally
via the serial bus registers. This can be controlled with
Register 0x57, Bits[7:6].
AVI Infoframes
The HDMI TMDS transmission contains infoframes with
specific information for the monitor such as:
•
•
•
•
•
•
•
•
Table 8. Output Formats
Port
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12-bit
1
Arrows indicate clock edge. The rising edge of clock = ↑, the falling edge = ↓.
Audio information
•
•
Audio sampling frequency
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
•
•
•
Video information
•
•
•
•
•
Vendor (transmitter source) name and product model
Two channels to eight channels of audio identified
Audio coding
CD
SACD
DVD
Video ID code (per CEA861B)
Color space
Aspect ratio
Horizontal and vertical bar information
MPEG frame information (I, B, or P frame)
23
DDR
DDR
CbCr [11:0]
↑
↓
22
G [3:0]
R [7:0]
1
21
Red/Cr [7:0]
CbCr [7:0]
20
19
DDR
↑
18
B [7:4]
17
16
Rev. 0 | Page 11 of 40
15
DDR
DDR
↑
↓
14
B [3:0]
G [7:4]
Bits D[23:0]
This information is the fundamental difference between DVI
and HDMI transmissions and is located in the read-only registers
Register 0x5A to Register 0xEE. In addition to this information,
registers are provided to indicate that new information has been
received. Registers with addresses ending in 7 or F beginning
with Register 0x87 contain the new data flags (NDF)
information. All of these registers contain the same information
and all are reset when any of them are read. Although there is
no external interrupt signal, it is very easy for the user to read
any of the NDF registers to see if there is new information to be
processed.
OUTPUT DATA FORMATS
The AD9393 supports 4:4:4, 4:2:2, double data-rate (DDR), and
BT656 output formats. Register 0x25[3:0] controls the output
mode. These modes and the pin mapping are illustrated in
Table 8.
13
Green/Y [7:0]
12
Y [7:0]
11
DDR 4:2:2
DDR 4:2:2
Y [11:0]
10
↑
↓
9
CbCr [11:0]
Y, Y [11:0]
8
7
6
DDR 4:2:2
5
Blue/Cb [7:0]
4
↑
CbCr
3
AD9393
2
↓
Y, Y
1
0