AD9393/PCBZ AD [Analog Devices], AD9393/PCBZ Datasheet - Page 23

• Manufacturer Part Number: AD9393/PCBZ
• Description: Low Power HDMI Display Interface
• Manufacturer: AD [Analog Devices]

0x25—Bit[1], Primary Output Enable
This bit places the primary output in active or high impedance
mode. The primary output is designated when using either 4:2:2
or DDR 4:4:4. In these modes, the data on the red and green
output channels (D[23:8]) is the primary output, whereas the
output data on the blue channel (D[7:0], DDR YCrCb) is the
secondary output. Double data rate 0 = primary output is in
high impedance mode. 1 = primary output is enabled. The
power-up default setting is 1.
0x25—Bit[0], Secondary Output Enable
This bit places the secondary output in active or high impe-
dance mode. The secondary output is designated when using
either 4:2:2 or DDR 4:4:4. In these modes, the data on the blue
output channel (D[7:0]) is the secondary output and the output
data on the red and green channels (D[23:8]) is the primary
output. Secondary output is always a DDR YCrCb data mode.
0 = secondary output is in high impedance mode. 1 = second-
ary output is enabled. The power-up default setting is 0.
0x26—Bit[7], Output Three-State
When enabled, this bit puts all outputs in a high impedance
state. 0 = normal outputs. 1 = all outputs in high impedance
mode. The power-up default setting is 0.
0x26—Bit[5], S/PDIF Three-State
When enabled, this bit places the S/PDIF audio output pins in a
high impedance state. 0 = normal S/PDIF output. 1 = S/PDIF
pins in high impedance mode. The power-up default setting is 0.
0x26—Bit[4], I
When enabled, this bit places the I
impedance state. 0 = normal I
high impedance mode. The power-up default setting is 0.
0x26—Bit[3], Power-Down Ball Polarity
This bit defines the polarity of the input power-down ball.
0 = power-down ball is active low. 1 = power-down ball is
active high. The power-up default setting is 1.
0x26—Bits[2:1], Power-Down Ball Function
These bits define the different operational modes of the power-
down ball. These bits are functional only when the power-down
ball is active; when it is inactive, the part is powered up and
functioning. 0x = the chip is powered down and all outputs are
in high impedance mode. 1x = the chip remains powered up,
but all outputs are in three-state outputs mode. The power-up
default setting is 00.
2
S Three-State
2
S output. 1 = I
2
S output pins in a high
2
S pins are in
Rev. 0 | Page 23 of 40
0x26—Bit[0], Power-Down
This bit is used to put the chip in power-down mode. In this
mode, the power dissipation is reduced to a fraction of the
typical power (see Table 2 for exact power dissipation). When
in power-down, the HSOUT, VSOUT, DCLK, and all 24 of the
data outputs are put into a high impedance state. Circuit blocks
that continue to be active during power-down include the
voltage references, sync detection, and the serial register. These
blocks facilitate a fast start up from power-down. 0 = normal
operation. 1 = power-down. The power-up default setting is 0.
0x27—Bit[7], Auto Power-Down Enable
This bit enables the chip to go into low power mode, or seek
mode if no sync inputs are detected. 0 = auto power-down
disabled. 1 = chip powers down if no sync inputs are present.
The power-up default setting is 1.
0x27—Bit[6], HDCP A0
This bit sets the LSB of the address of the HDCP I
to 1 only for a second receiver in a dual-link configuration. The
power-up default is 0.
0x27—Bit[5], Clock Test
The power-up default setting is 0.
2
C. Set this bit
AD9393