AD9393/PCBZ AD [Analog Devices], AD9393/PCBZ Datasheet - Page 13

• Manufacturer Part Number: AD9393/PCBZ
• Description: Low Power HDMI Display Interface
• Manufacturer: AD [Analog Devices]

Hex Address
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
Read/Write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read
Read
Bits
[7]
[5]
[4]
[3]
[2:1]
[0]
[7]
[6]
[5]
[4]
[3]
[2:0]
[7:2]
[1:0]
[7:0]
[3:0]
[7:0]
[3:0]
[7:0]
[7]
[6:5]
[4:0]
[6]
[5]
[4]
[3]
[2:0]
[6]
[5]
[4]
[3:0]
Default
Value
0xxxxxxx
xx0xxxxx
xxx0xxxx
xxxx1xxx
xxxxx00x
xxxxxxx0
1xxxxxxx
x0xxxxxx
xx0xxxxx
xxx0xxxx
xxxx0xxx
xxxxx000
011000xx
xxxxxx01
00000100
xxxx0101
00000000
xxxx0010
11010000
0xxxxxxx
x00xxxxx
xxx11000
x0xxxxxx
xx0xxxxx
xxx0xxxx
xxxx0xxx
xxxxx000
x0xxxxxx
xx0xxxxx
xxx0xxxx
xxxx0000
Register Name
Output three-state
S/PDIF three-state
I
Power-down ball polarity
Power-down ball function
Power-down
Auto power-down enable
HDCP A0
Clock test
BT656 EN
Force DE generation
Interlace offset
VSYNC delay
HSYNC delay MSB
HSYNC delay LSB
Line width MSB
Line width LSB
Screen height MSB
Screen height LSB
CTRL EN
I
I
TMDS sync detect
TMDS active
AV mute
HDCP keys read
HDMI quality
HDMI content encrypted
HDMI HSYNC polarity
HDMI VSYNC polarity
HDMI pixel repetition
2
2
2
S three-state
S output mode
S bit width
Rev. 0 | Page 13 of 40
Description
Three-state the outputs.
Three-state the S/PDIF output.
Three-state the I
Sets polarity of power-down ball.
0 = active low.
1 = active high.
Selects the function of the power-down ball.
0x = power-down.
1x = three-state outputs.
0 = normal.
1 = power-down.
0 = disable auto low power state.
1 = enable auto low power state.
Sets the LSB of the address of the HDCP I2C. Set to 1 only
for a second receiver in a dual-link configuration.
Must be written to 0.
Enables EAV/SAV codes to be inserted into the video
output data.
Allows use of the internal DE generator—not the DE
transmitted over TMDS.
Sets the difference (in HSYNCs) in field length between
Field 0 and Field 1.
Sets the delay (in lines) from the VSYNC leading edge to
the start of active video.
HSYNC delay MSB of Register 0x29.
Sets the delay (in pixels) from the HSYNC leading edge to
the start of active video.
Line width MSB of Register 0x2B.
Sets the width of the active video line in pixels.
Screen height MSB of Register 0x2D.
Sets the height of the active screen in lines.
Allows CTRL[3:0] to be output on the I
00 = I
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
Sets the desired bit width for right-justified mode.
Detects a TMDS DE.
Detects a TMDS clock.
Gives the status of AV mute based on general control
packets.
Returns 1 when read of EEPROM keys is successful.
Returns quality number based on DE edges.
This bit is high when HDCP decryption is in use (content is
protected). The signal goes low when HDCP is not being
used. Use this bit to allow copying of the content. The bit
should be sampled at regular intervals because it can
change on a frame-by-frame basis.
Returns HDMI HSYNC polarity.
Returns HDMI VSYNC polarity.
Returns current HDMI pixel repetition amount. 0 = 1×,
1 = 2× … The clock and data outputs are automatically
decimated by this value.
2
S mode.
2
S output and the MCLK output.
2
S data pins.
AD9393