ISD-200 ETC2 [List of Unclassifed Manufacturers], ISD-200 Datasheet - Page 57

• Manufacturer Part Number: ISD-200
• Description: USB Mass Storage Class Bulk-Only Specification Compliant
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Address
ISD-200 ASIC Datasheet
Appendix A – Example EEPROM or FBh Data Contents
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Data Signature (LSB)
Data Signature (MSB)
Event Notification
DPLL Parameters
ATA Initialization
Timeout
Reserved – Bits [7:6]
Master/Slave Selection –
Bit [5]
ATAPI DEVICE RESET –
Bit [4]
ATA Timing – Bits [3:0]
ATA Command
Designator (Byte 0, LSB)
Field Name
This field specifies the least significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
This field specifies the most significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
field to 0x00 disables this feature.
POR configuration default of 0x00
This field denotes the parameters used by the internal DPLL. The original
clock source is 12 MHz.
5 bits M (7:3), 2 bits N (2:1), 1 bit Enable (0). When enabled, multiply the
original clock source by M, divided by N
M:
N:
Enable:
POR configuration default of 0x00
This field specifies the time in multiples of 128 ms (0x19 = 3.2s) before
the ISD-200 stops polling the Alternate Status device register for reset
complete and restarts the reset process.
NOTE: The ROM contents ATA Initialization Timeout value must be
large enough to accommodate I_MODE operation during the first device
initialization sequence (before FBh configuration data load)
POR configuration default of 0x02
This field specifies the value in CBW CB field that designates if the CB is
decoded as ATA commands instead of the ATAPI command block.
POR configuration default of 0x00
This field specifies the ATA event notification command. Setting this
Reserved; set to ‘0’
This bit specifies device number selection.
“0” - Drive 0
“1” - Drive 1
This bit specifies that the ISD-200 perform a ATAPI DEVICE RESET
command during a full initialization sequence.
This field determines ATA Bus data access cycle times.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
POR configuration default of 0x0B
In-System Design Confidential
00000 => M=1
00001 => M=1
00010 => M=2
00011 => M=3
11111 => M=31
00 => N=1
01 => N=3
10 => N=2
11 => N=4
0 => CLK_N disabled
1 => CLK_N enabled
….
reserved
Mode 2 (292 ns)
Mode 2 (333 ns)
Mode 2 (375 ns)
Mode 1 (458 ns)
Mode 1 (500 ns)
Mode 1 (542 ns)
Mode 1 (583 ns)
Mode 0 (625 ns)
Mode 0 (666 ns)
Mode 0 (708 ns)
Mode 0 (750 ns)
reserved
reserved
reserved
reserved
Description
SROM / FBh
Example
0xFC
Data
0x52
0x48
0x43
0x02
0x01
0x24
55