HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 204

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.2 Register Descriptions (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 8-4.
Table 8-4 Selection of Short and Full Address Modes
Channel
0
1
8.2.1 Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0), and as a source address register otherwise.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.2.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
Bit
Initial value
Read/Write
31
—
1
Bit 2
DTS2A
1
Other than above
1
Other than above
30
—
1
29
—
1
MARR
28
—
1
27
—
1
Bit 1
DTS1A
1
1
26
—
1
25
—
1
24
—
1
R/W
23
Description
DMAC channel 0 operates as one channel in full address mode
DMAC channels 0A and 0B operate as two independent channels
in short address mode
DMAC channel 1 operates as one channel in full address mode
DMAC channels 1A and 1B operate as two independent channels
in short address mode
R/W
22
R/W
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
190
R/W
17
Undetermined
R/W
16
R/W
15
R/W
14
R/W
13
R/W
MARH
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0