MK50H25 STMICROELECTRONICS [STMicroelectronics], MK50H25 Datasheet
MK50H25
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MK50H25 Summary of contents
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... SECTION 1 - FEATURES System clock rate MHz (MK50H25 - 33), 25 MHz (MK50H25 - 25 MHz (MK50H25 - 16). Data rate Mbps continuous (MK50H25 - 33 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate 13.3 Mbytes/sec us- ing optional 5 SYSCLK DMA cycle (150 nS MHz SYSCLK ...
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... Z8000, Z80, 8086, 8088, 80186, 80286, 80386SX, etc. The MK50H25 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user program- mable I/O pins ...
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... PLCC52 PIN CONNECTION (Top view DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/ DAL13 DAL14 DAL15 A16 A17 A18 MK50H25Q A19 A20 A21 A22 No Connect A23 MK50H25 3/64 ...
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... READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK50H25 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. ...
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... BUSAKO is a bus request daisy chain output. If MK50H25 is not requesting the bus and it receives HLDA, BUSAKO will be driven low. If MK50H25 is requesting the bus when it receives HLDA, BUSAKO will remain high Note: All transfers are entire word unless the MK50H25 is configured for 8 bit operation. Pin 17 is configured through bit 0 of CSR4. ...
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... DESCRIPTION As a Bus Slave, the MK50H25 asserts READY when it has put data on the DAL lines during a READ cycle or is about to take data from the DAL lines during a WRITE cycle. READY is a response to DAS and it will be released after DAS negated ...
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... Figure 1: Possible System Configuration for thr MK50H25 MEMORY (MULTIPLE DATA BLOCKS) HOST PROCESSOR (68000, 80186, Z8000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL MK50H25 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA COMM. CONNECTOR (SUCH AS RS-449, RS-232C, V.35) ...
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... MK50H25 Figure 2: MK50H25 Simplified Block Diagram DMA CONTROLLER SYSCLK RECEIVER FIFO RCLK RECEIVER RD 8/64 READY READ DAS FIRMWARE CONTROL / STATUS MICRO REGISTERS CONTROLLER INTERNAL BUS TRANSMITTER FIFO VCC VSS - GND RESET TCLK TRANSMITTER TD LOOPBACK TEST ROM TIMERS ...
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... This programmability , along with the programmable burst length of the DMA controller, enables the user to define how often and for how long the MK50H25 must use the host bus. For more information, see CSR4. For example, if the watermark level is set at 34 ...
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... MK50H25 is allowed and commanded to transmit the buffer. When the MK50H25 does not own the buffer, it will not transmit that buffer. For receive, when the MK50H25 owns a buffer, it may place received data into that buffer. Con- versely, when the MK50H25 does not own a re- ceive buffer, it will not place received data into that buffer ...
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... The Command/Response Repertoire The command/response MK50H25 is shown in Tables A and B. This set conforms to the 1984 & 1988 CCITT X.25, plus support of XID, Test, and UI frames conforming to ISDN LAPD. The MK50H25 will process the In- formation, Supervisory, and Unnumbered frames shown in Tables A and B, and will handle the A and C fields for all I and UI frames ...
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... MK50H25 Table A - MK50H25 Command/Response Repertoire FORMAT COMMAND Information Transfer I Supervisory RR RNR REJ * Unnumbered UI SABM DISC * XID TEST Table B - MK50H25 Command/Response Repertoire FORMAT COMMAND RESPONSE ENCODING Information I I Transfer Supervisory RR RR RNR RNR REJ REJ Unnumbered SABME All Others All Others Notes: 1 ...
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... Figure 3: MK50H25 Memory Management Structure CSR 2, CSR3 POINTER TO INITIALIZATI ON BLOCK INITIALIZATI ON BLOCK MODE FRAME ADDRESS FIELDS TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINT ER XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TEST RECEIVE DESCRIPTOR POINTER STATUS BUFFER ADDRESS ERROR COUNTERS STATUS BUFFER XID/T EST RECEIVE BUFFER ...
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... MK50H25. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the MK50H25. CSR’s are accessed through two bus address- able ports, an address port (RAP), and a data port (RDP), thus requiring only two locations in the system memory or I/O map ...
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... NAME 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the data from the CSR selected in RAP CSR DATA DESCRIPTION MK50H25 15/64 ...
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... MK50H25’s response to a Transmit Descriptor Ring entry insertion by the host. TDMD is written with ONE ONLY and cleared by the MK50H25 microcode after it is used. It may read as a ”1” for a short time after it is written because the microcode may have been busy when TDMD was set also cleared by Bus RESET. Writing a ” ...
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... PRIMITIVE INTERRUPT is set after the chip updates the primitive register to issue a provider primitive. When PINT is set, an interrupt is generated if INEA =1. PINT is READ/CLEAR ONLY and is set by MK50H25 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect also cleared by Bus RESET or by issuing a Stop primitive. 02 ...
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... I, UI, or FRMR frame, and any good frame in Transparent Mode. When RINT is set, an interrupt is generated if INEA = 1. RINT is READ/CLEAR ONLY and is set by the MK50H25 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect cleared by Bus RESET or by issuing a Stop primitive. ...
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... Valid only after receiving Reset Indication primitive. In Transparent Mode or Disconnected Phase, it instructs the MK50H25 to stop the T1 timer. 10 XID Request: Instructs the MK50H25 to send a XID frame to the remote station. Data in the XID/Test Transmit buffer is used for the Data Field. Invalid in Stopped Mode. 11 XID Response: Instructs the MK50H25 to send an XID response frame to the remote station ...
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... Host responses are Connect Response or Disconnect Request. 5 Remote Busy Indication: Indicates change in the Remote Busy status of the MK50H25. See PPARM table for specific conditions. This primitive is only generated if RBSY (bit 11 of IADR+16) is set = 1. 6 Connect Indication: Indicates attempt by the Primary station to establish a logical link (SABM received) ...
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... SYSCLKs for single DMA). See Figures 7a and 8a for details. 14 EIBEN Extended Initialization Block Enable. Setting this bit will cause the MK50H25 to use an extended Initialization Block which uses all of IADR+ 16-bit scaler, moves N2 to the upper byte of IADR+40, and extends the Init Block past IADR+55. This bit is READ/WRITE. 13 ...
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... XWD1/RWD1 11 ROBA Setting this bit will cause the MK50H25 to put the first byte of received data into both the upper and lower bytes of the receive buffer to effec- tively cause the Receive data to be Odd-Byte Aligned. This feature is particularly useful for extraction of odd-byte Level 3 headers from re- ceived frames leaving the remaining data even byte aligned ...
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... FWM These bits define the FIFO watermarks. FIFO watermarks prevent the MK50H25 from performing DMA transfers to/from the data buffers until the FIFOs contain a minimum amount of data or space for data. For re- ceive, data will only be transferred to the buffers after the FIFO has at least N 16-bit words or end of frame has been reached ...
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... RTS/CTS ENABLE is a READ/WRITE bit used to configure pins 26 and 30. If this bit is set, pin 26 becomes RTS and pin 30 becomes CTS. RTS is driven low whenever the MK50H25 has data to trans- mit and is kept low during transmission. RTS will be driven high after the closing flag of a signal unit is transmited if either no other frames are in the FIFO or if the minimum signal unit spacing is higher than 2 (see Mode Register) ...
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... DATA SET READY is used to control or observe the DSR I/O pin depending on the value of DSRD. If DSRD = 0, this bit be- comes READ ONLY and always equals the current value of the DSR/CTS pin. If DSRD = 1 this bit becomes READ/WRITE and any value written to this bit appears on the DSR/CTS pin. MK50H25 25/64 ...
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... MK50H25 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, portions of the Initialization block are read by the MK50H25. The remainder of the Initialization block will be read as needed by the MK50H25. ...
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... Mode Register The Mode Register allows alteration of the MK50H25’s operating parameters MFS IADR + 00 <4:0> BIT NAME DESCRIPTION 15:11 MFS<4:0> Minimum Frame Spacing defines the minimum number of flag sequences transmitted MK50H25. This only affects frames transmitted by the MK50H25 and does not restrict the spacing of the frames received by the MK50H25 ...
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... In this case, it will treat a frame received with a global address as a comand, whether or not XID/TEST frame. The MK50H25 however, will transmit a frame with a global ad- dress if all 1’s have been placed in the appropriate Local/Remote Address fields prior to an Init primitive (UPRIM=2, CSR1) being issued ...
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... Table 2 and Table 3. If EXTC is 0 then the C-field is one octet for all frames. If however EXTC is set to 1, the MK50H25 will look to see if either of the two least significant bits of the C-field so, the frame is said to have an extended control field which is two octets. In addition, bits EXTAF and EXTCF (Mode Register bit 09 & ...
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... MK50H25 Table 3: Address and Control Field Handling By The MK50H25 Receiver In Transparent Mode DACE PROM EXTA EXTAF EXTC ...
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... MAXIMUM RETRANSMISSION COUNT. This field must contain the two’s complement of one less than the maximum number of retransmissions that will be made following the expiration of T1. If CSR2<14> bit EIBEN=1 then the MK50H25 will expect the value for counter located in the upper byte of IADR + 40. ...
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... MK50H25 TP TRANSMIT POLLING TIMER. This scaled timer determines the length of time between polls of the Transmit Descriptor Ring to determine if there is a frame awaiting transmis- sion (i.e. OWNA bit has been set plus other appropriate information placed in the current Transmit Descriptor). Unless TDMD (see CSR0) is set frame is received (in proto- col mode) on the link, no attempt is made to transmit a frame in the Transmit Descriptor Ring until TP expires ...
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... FCSER. Setting this bit enables a separate Error Counter at IADR + 56 that will count aborted frames separately from Bad Frames Received. 08 FCSEN Setting this bit will cause the MK50H25 to append the entire FCS of received frames to the receive data buffer, and MCNT will reflect the additional FCS bytes. 07:00/15:00 ...
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... MK50H25 14:12 TLEN TRANSMIT RING LENGTH is the number of entries in the Transmit Ring expressed as a power of two Reserved, must be written as a zero. 10:08 TWD Transmit Window is the window size of the Transmitter expressed as a power of two less one. TWD is the maximum number of I frames which may be transmitted without an acknowledgement ...
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... Error Counters Seven locations in the Initialization buffer are reserved for use as error counters which the MK50H25 will increment. These counters are intended for use by the host CPU for statistical analysis. The MK50H25 will only increment the counters the user to clear and preset them. The error counters are: ...
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... BIT NAME DESCRIPTION 15:00 BCNT Buffer Byte Count is the length of the buffer pointed to by this descriptor expressed in two’s complement. This field is written to by the Host and unchanged by MK50H25. The value of BCNT must be an even number. 36/ ...
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... Message Byte Count is the length, in bytes, of the received frame MCNT is valid only when ELF is set to a one. MCNT is written by MK50H25 and read by the Host. If ELF is set to a zero the entire buffer has been utilized and the message byte count is given in BCNT above. The value of this field is expressed in two’s comple- ment ...
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... BIT NAME DESCRIPTION 15:00 TBADR The Low Order 16 address bits of the buffer pointed to by this descriptor. TBADR is written by the Host and unchanged by MK50H25. The least significant bit is zero since the descriptor must be word aligned. 4.3.2.3 Transmit Message Descriptor 2 (TMD2 BIT ...
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... SBA + 10 SBA + MCNT<15:00> V(r) Local State Remote State Phase CURRD <23:16> CURRD <15:00> Reserved CURXD <23:16> CURXD <15:00> MK50H25 V(s) V(A) 39/64 ...
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... Setup the Initialization Block and Desciptor Rings. 3. Load the address of the initialization block information into CSR’s 2 and 3. 4. Issue the INIT primitive through CSR1 (write 4200H to CSR1) instructing the MK50H25 to read the initialization block pointed to by CSR’s 2 and 3. 5. Wait for the INIT confirmation primitive (CSR1 = 0242H) from the MK50H25. ...
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... The following procedure should be followed when refusing link establishment Connect Indication primitive received indicates a request by the remote station to establish a link. 2. Issue a Disconnect Request primitive to refuse to establish the link (causes MK50H25 to respond with DISC frame depending on value of UPARM). 4.4.5 Sending Data Use the following procedure to send a frame: 1 ...
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... Issue the STOP primitive through CSR1. This will disable the MK50H25 from receiving or transmitting. The TD pin will be held high while the MK50H25 is in the Stopped mode. The STOP bit in CSR0 will be set and interrupts will be disabled. If reception or transmission of a frame is in progress, then re- ceived data may be lost, and the transmitted frame will be aborted ...
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... Otherwise Failed device the PAV bit is not set within 75 msec (SYSCLK = 10MHZ), then the MK50H25 is unable to respond to the Self Test Request and will not complete successfully. If the self test passes, then after clearing the PAV bit it may be immediately reexecuted from step 3, oth- erwise re-execution should proceed from step 1 ...
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... T TD data hold time after TDH the falling edge of TCLK SECTION 5 Parameter Parameter Parameter -16 Test Condition Min MK50H25 Value Unit -25 to +100 C -65 to +150 0.5 W Min. Typ. Max. Units -0.5 +0.8 V +2 ...
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... MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time RCH 15 RCLK T RCLK low time RCL 16 RCLK T Rise time of RCLK RCR 17 RCLK T Fall time of RCLK RCF ...
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... AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO T DALO hold time (Bus Master read) ROH hold time CSH setup time ...
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... MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time RCH 15 RCLK T RCLK low time RCL 16 RCLK T Rise time of RCLK RCR 17 RCLK T Fall time of RCLK RCF ...
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... AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO T DALO hold time (Bus Master read) ROH hold time CSH setup time ...
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... MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time RCH 15 RCLK T RCLK low time RCL 16 RCLK T Rise time of RCLK RCR 17 RCLK T Fall time of RCLK RCF ...
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... AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO T DALO hold time (Bus Master read) ROH hold time CSH setup time ...
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... Figure 5a: TTL Output Load Diagram TEST POINT FROM OUTPUT UNDER TEST 0 NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK50H25 Serial Link Timing Diagram RCLK RD TCLK 12 TD TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES, UNLESS OTHERWISE SPECIFIED: OUTPUT INPUT FLOAT ...
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... Figure 7: MK50H25 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15, CYCLE =1 to select the shorter DMA cycle as shown in Figure 7a. ...
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... MK50H25 Figure 7a: MK50H25 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE =1. 2. Output delay times are the maximum delay from the specifed edge to a valid output. ...
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... Figure 8: MK50H25 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15, CYCLE =1 to select the shorter DMA cycle as shown in Figure 8a. ...
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... MK50H25 Figure 8a: MK50H25 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) SYSCLK HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This Reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE = 1. Times T0 and T5 from the standard DMA Cycle are removed for this reduced timing. ...
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... Figure 8b: BUS Master BURST Timing (Reduced Cycle - Write SYSCLK 64 HOLD 24 25 HLDA 27 A 16-23 23 ALE 23 DAS READY 29 DAL0-15 ADDR 33 DALO 45 DALI READ BM0 ADDRESS DATA ADDR MK50H25 ADDRESS DATA 48 48 56/64 ...
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... MK50H25 Figure 9: MK50H25 BUS Slave Timing Diagram (Read) SYSCLK CS ADR DAS READY READ (Read) DAL 0-15 NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. Output delay times are from the specified edge to a valid output. ...
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... Figure 10: MK50H25 BUS Slave Timing Diagram (Write) SYSCLK CS ADR DAS READY READ (Write) DAL0-15 NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. Output delay times are from the specified edge to a valid output. ...
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... MK50H25 ORDERING INFORMATION MK50H25 Q XX PACKAGE N = Plastic DIP (48 Pins Plastic J-Leaded Cip Carrier (52 Pins) -84Q = 84 PLCC for use with external ROM PART# PROTOCOL 50H25 = LAPB 59/64 SPEED SORT 16 = 16MHz SYSCLK 25 = 25MHz SYSCLK 33 = 33MHz SYSCLK ...
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... DIP48 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 58. 4.445 L mm MAX. MIN. 0.31 0.009 62.74 16.68 0.598 14.1 3.3 MK50H25 inch TYP. MAX. 0.025 0.018 0.012 0.050 2.470 0.657 0.100 2.300 0.555 0.175 0.130 60/64 ...
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... MK50H25 PLCC52 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 19.94 D1 19.05 D2 17.53 D3 15.24 E 19.94 E1 19.05 E2 17.53 E3 15.24 e 1.27 L 0.64 L1 1.53 M 1.07 M1 1.07 61/64 mm MAX. MIN. 5.08 3.30 0.53 0.81 0.01 20.19 19.20 18.54 0.60 20.19 19.20 18.54 0.60 0.05 1.22 1.42 inch TYP. MAX. 0.165 0.20 0.020 0.090 0.13 0.013 0.021 0.026 0.032 0.785 0.795 0.750 0.756 0.690 0.730 0.785 0.795 0.750 0.756 0.690 ...
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... A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 30.10 D1 29.21 D2 27.69 D3 25.40 E 30.10 E1 29.21 E2 27.69 E3 25.40 e 1.27 L 0.64 L1 1.53 M 1.07 M1 1.07 mm MAX. MIN. 5.08 3.30 0.53 0.81 0.01 30.35 29.41 28.70 1.00 30.35 29.41 28.70 1.00 0.05 1.22 1.42 MK50H25 inch TYP. MAX. 0.165 0.20 0.020 0.090 0.13 0.013 0.021 0.026 0.032 1.185 1.195 1.150 1.158 1.090 1.130 1.185 1.195 1.150 1.158 1.090 1.130 0.025 0.060 0.042 0.048 0.042 0.056 62/64 ...
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... MK50H25 MK50H25 PLCC84 Pin Description PIN SIGNAL NAME 1 Vss 2 EROMEN - External ROM Enable 3 DAL07 DAL06 6 EROMD11 7 DAL05 8 DAL04 9 DAL03 10 EROMD10 11 DAL02 12 DAL01 13 DAL00 14 EROMD09 15 READ 16 EROMD08 17 INTR 18 DALI 19 DALO Vss EROMD07 24 DAS 25 EROMD06 26 BM0 27 EROMD05 28 BM1 29 HOLD 30 EROMD04 ...
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... SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. MK50H25 64/64 ...