MK50H25 STMICROELECTRONICS [STMicroelectronics], MK50H25 Datasheet - Page 49

no-image

MK50H25

Manufacturer Part Number
MK50H25
Description
HIGH SPEED LINK LEVEL CONTROLLER
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK50H25N-25
Manufacturer:
ROHM
Quantity:
3 305
Part Number:
MK50H25N-25
Manufacturer:
ST
0
Part Number:
MK50H25N-25REVB01
Manufacturer:
ST
Quantity:
6
Part Number:
MK50H25Q-10
Manufacturer:
ST
Quantity:
12 388
Part Number:
MK50H25Q-16
Manufacturer:
ST
Quantity:
12 388
Part Number:
MK50H25Q-25
Quantity:
5 510
Part Number:
MK50H25Q-25
Manufacturer:
ST
0
Part Number:
MK50H25Q-33
Manufacturer:
ST
0
MK50H25
AC TIMING SPECIFICATIONS (Continued) - MK50H25 -33
T
49/64
No
13
14
15
16
17
18
19
20
21
22 ALE/DAS
23 ALE/DAS
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 DALI / DALO
46
47
48
A
= 0 C to 70 C, V
BM)/BM1
Signal
RCLK
RCLK
RCLK
RCLK
RCLK
HLDA
HLDA
HLDA
DALI
DALI
DALI
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAL
DAS
DAS
ALE
ALE
ALE
RD
RD
RD
RD
A
A
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SWDH
SWDS
BMDE
BMDD
DOFF
HLAH
RDAS
RDAH
SRDS
SRDH
DASS
DASH
HLAS
ALES
ALHB
ALHS
WDH
RCH
RCR
RDR
RDH
RDS
DON
HHA
WAH
WDS
RCT
RCL
RCF
RDF
XAS
XAH
RIS
RIH
AS
AH
CC
= +5 V 5 percent, unless otherwise specified.
RCLK period
RCLK high time
RCLK low time
Rise time of RCLK
Fall time of RCLK
RD data rise time
RD data fall time
RD hold time after rising edge of RCLK
RD setup time prior to rising edge of
RCLK
Bus Master driver disable
Bus Master driver enable after rising
edge T1 SYSCLK
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
HLDA input setup time
Delay to rising edge HLDA from rising
edge HOLD
Address setup time
Address hold time
Address setup time
Address hold time
Data setup time (Bus Master read)
Data hold time (Bus Master read)
Address hold time (Bus Master write)
Data setup time (Bus Master write)
Data hold time (Bus Master write)
Data setup time (Bus Slave read)
Data hold time (Bus slave read)
Data hold time (Bus slave write)
Data setup time (Bus slave write)
ALE setup time
ALE hold time (asserted to de-
asserted) (DMA Burst)
ALE hold time (asserted to 3-State)
(Single DMA cycle)
DAS setup time from falling edge of T2
SYSCLK (Bus Master)
DAS hold time from rising edge of
SYSCLK (Bus Master)
Bus Master driver enable (from 3-
State to driven) (Bus Master)
DALI setup time (Bus Master read)
DALI hold time (Bus Master read)
Bus Master driver disable (from driven
to 3-State) (Bus Master)
Parameter
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Notes
Min.
20
10
10
13
10
10
8
8
0
0
0
0
2
8
0
0
0
0
8
5
MK50H25 -33
Typ.
Max.
20
20
25
20
30
20
15
25
25
25
25
25
15
20
20
15
20
15
20
20
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for MK50H25