HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 425

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HD6437101

Manufacturer Part Number
HD6437101
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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(2) Exiting High-Impedance State
The MMT output pins that have entered the high-impedance state by the input level detection are
released from this state by restoring them to their initial states by means of a power-on reset, or by
clearing all the POE flags in ICSR2 (POE4F to POE6F: bits 12 to 14).
13.8.5
To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE
pin.
P
Sampling clock
PUOA
All low-level samples
At least one high-level
sample
Note: The other MMT output pins also enter the high-impedance state at the same timing.
input
Usage Note
Figure 13.18 Low Level Detection Operation
[1]
[1]
128 clocks
8, 16, or
[2]
[2]
Rev.1.00 Sep. 18, 2008 Page 391 of 522
[3]
Section 13 Motor Management Timer (MMT)
[16] Flag set (POE accepted)
[13]
High-impedance state
Flag not set
REJ09B0069-0100

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