LT3434 LINER [Linear Technology], LT3434 Datasheet - Page 15

• Manufacturer Part Number: LT3434
• Description: High Voltage 3A, 200kHz Step-Down Switching Regulator with 100uA Quiescent Current
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
limits the switch current via the V
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C
regulated output voltage determines the output voltage
ramp rate. When the current through the C
exceeds the C
output capacitor is limited by reducing the V
The C
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3434 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3434 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. In addition, V
currents are reduced to typically 45µA and 125µA respec-
tively during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT3434 operates in sleep mode increases and the
dV
dt
SS
1V/DIV
=
V
OUT
threshold is proportional to the FB voltage (see
I
C
CSS
SS
V
V
I
LOAD
IN
OUT
C
CSS
= 12V
SS
= 3.3V
= 500mA
= 1000pF
threshold (I
U
Figure 4. V
C
CSS
= 0.01µF
U
1ms/DIV
CSS
OUT
), the voltage ramp of the
dV/dt
IN
W
and BIAS quiescent
C
C
pin to maintain a
CSS
= 0.1µF
SS
3434 F04
C
SS
pin voltage.
pin to the
U
capacitor
average input current is greatly reduced resulting in higher
efficiency.
The minimum average input current depends on the V
V
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
where
Example: For V
During the sleep portion of the Burst Mode cycle, the V
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
I
IN AVG
OUT
(
I
V
V
I
I
I
η = low current efficiency (non Burst Mode operation)
I
IN AVG
VINS
BIASS
FB
S
OUT
IN
(
= catch diode reverse leakage at V
ratio, V
= feedback network current
= input voltage
)
=
=
= input pin current in sleep mode
= output voltage
= BIAS pin current in sleep mode
)
45
45
150
125
100
≅
75
50
25
0
µ + µ +
µ + µ +
C
I
0
VINS
A
A
frequency compensation, feedback divider
OUT
5
5
10
+
= 3.3V, V
A
A
I
SHDN
Figure 5. I
INPUT VOLTAGE (V)
20
⎛
⎜
⎝
44
3 3
12
+
.
µ =
30
A
⎛
⎜
⎝
IN
⎞
⎟
⎠
Q
V
(
= 12V
V
125
OUT
vs V
99
IN
40
µ
µ +
V
IN
⎞
⎟
⎠
OUT
A
A
(
50
I
= 3.3V
BIASS
OUT
3434 F05
12 5
(
0 85
.
.
60
LT3434
( )
µ +
+
η
)
A
I
FB
15
0 5
+
.
I
S
IN
µ
3434f
)
A
to
C
)