LT3434 LINER [Linear Technology], LT3434 Datasheet - Page 18

• Manufacturer Part Number: LT3434
• Description: High Voltage 3A, 200kHz Step-Down Switching Regulator with 100uA Quiescent Current
• Manufacturer: LINER [Linear Technology]

LT3434
APPLICATIO S I FOR ATIO
Example:
See the Typical Performance Characteristics section for
graphs of SHDN and V
V
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between 30% and 70% to the LT3434 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to 700kHz. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (230kHz), not the typical oper-
ating frequency of 200kHz. Caution should be used when
synchronizing above 230kHz because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
18
OUT
R
R
R2 =
1
3
R3
=
=
=
1 5 5
1.3M
408
5 1 3
7 – 1.3
.
12 2
(
R1
R2
(
15
.
4
k
–
1
µ
LT3434
M
Ω
(Nearest 1% 412k)
V
SHDN
Figure 8. Undervoltage Lockout
A
IN
Ω
)
–
3µA
)
=
1
U
1.3
µ
=
1 3
A
2.4V
1.3V
.
6 5
IN
.
–
M
M
currents verses input voltage.
6 49
U
Ω
+
–
+
–
.
COMP
COMP
Ω
SHDN
1 3
V
IN
.
(Nearest 1% 6.49M )
M
Ω
W
U
ENABLE
Ω
3434 F08
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid and
hazardous conditions for the SW pin.
If no synchronization is required this pin should be con-
nected to ground.
POWER GOOD
The LT3434 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB is taken above V
the C
the PGFB pin drops below V
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
delay time between the PGFB pin exceeding its threshold
(V
When the PGFB pin rises above V
(I
voltage on the external capacitor reaches an internal clamp
(V
resultant PG delay time is given by t = C
the voltage on the PGFB pin drops below its V
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
several different configurations for the LT3434 Power
Good circuitry.
CT
PGFB
CT
) from the C
), the PG pin becomes a high impedance node. The
T
) and the PG pin set to a high impedance state.
pin starting the delay period. When the voltage on
T
pin into the external capacitor. When the
PGFB
T
pin determines the amount of
, current (I
T
PGFB
= 0.1µF. Figure 10 shows
PGFB
the C
CSS
current is sourced
CT
) is sourced into
T
• (V
pin is rapidly
T
PGFB
PGFB
pin will be
CT
)/(I
, C
. When
CT
CT
). If
will
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