LT3434 LINER [Linear Technology], LT3434 Datasheet - Page 6

• Manufacturer Part Number: LT3434
• Description: High Voltage 3A, 200kHz Step-Down Switching Regulator with 100uA Quiescent Current
• Manufacturer: LINER [Linear Technology]

LT3434
TYPICAL PERFOR A CE CHARACTERISTICS
PI FU CTIO S
NC (Pin 1): No Connection.
SW (Pins 2, 5): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum nega-
tive switch voltage allowed is –0.8V.
V
NPN switch. V
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
6
IN
U
(Pins 3, 4): This is the collector of the on-chip power
U
500mA/DIV
50mV/DIV
50mV/DIV
IN
1A/DIV
V
V
I
I
OUT
OUT
OUT
OUT
powers the internal control circuitry when
Burst Mode Operation
V
V
I
No Load 2A Step Response
V
V
C
Q
CE
IN
OUT
IN
OUT
OUT
U
= 100µA
= 12V
= 12V
voltage across the internal NPN.
= 3.3V
= 3.3V
= 100µF
IN
pin through the input bypass
W
500µs/DIV
5ms/DIV
U
3434 G14
3434 G17
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.1Ω FET
structure.
C
of delay time between the PGFB pin exceeding its thresh-
old (V
When the PGFB pin rises above V
from the C
age on the external capacitor reaches an internal clamp
(V
resultant PG delay time is given by t = C
T
CT
500mA/DIV
(Pin 7): A capacitor on the C
50mV/DIV
50mV/DIV
), the PG pin becomes a high impedance node. The
1A/DIV
PGFB
V
V
I
I
OUT
OUT
OUT
OUT
V
V
I
V
V
C
I
Burst Mode Operation
Step Response
T
Q
LOAD(DC)
) and the PG pin set to a high impedance state.
IN
OUT
IN
OUT
OUT
= 100µA
pin into the external capacitor. When the volt-
= 12V
= 12V
= 3.3V
= 3.3V
= 100µF
= 500mA
500µs/DIV
5µs/DIV
T
pin determines the amount
PGFB
3434 G15
3434 G18
, current is sourced
CT
• V
CT
/I
CT
. If the
3434f