ADL5356-EVALZ AD [Analog Devices], ADL5356-EVALZ Datasheet - Page 22

• Manufacturer Part Number: ADL5356-EVALZ
• Description: 1200 MHz to 2500 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun
• Manufacturer: AD [Analog Devices]

ADL5356
Table 7. Evaluation Board Configuration
Components
C1, C8, C10, C12,
C13, C15, C18,
C21, C22, C23,
C24, C25, C26
Z1 to Z4, C2, C3,
C6, C7, C9, C11
T1, T2, C17, C19,
C20, C27 - C33,
L1, L2, L4, L5,
R3, R6, R9, R10
C14, C16,
R15, LOSEL
R19, PWDN
R1, R2, R4, R5, L3,
L6, R7, R8, R11 to
R14, R16, R17, C34
Figure 55. Evaluation Board Top Layer
Description
Power Supply Decoupling. Nominal supply decoupling consists of a
0.01 μF capacitor to ground in parallel with 10 pF capacitors to
ground positioned as close to the device as possible.
RF Main and Diversity Input Interface. Main and diversity
input channels are ac-coupled through C9 and C11. Z1 to
Z4 provide additional component placement for external
matching/filter networks. C2, C3, C6, and C7 provide bypassing
for the center taps of the main and diversity on-chip input baluns.
IF Main and Diversity Output Interface. The open collector IF
output interfaces are biased through pull-up choke inductors
L1, L2, L4, and L5, with R3 and R6 available for additional
supply bypassing. T1 and T2 are 4:1 impedance transformers
used to provide a single-ended IF output interface with C27
and C28 providing center-tap bypassing. C17, C19, C20, C29,
C30, C31, C32, and C33 ensure an ac-coupled output interface.
Remove R9 and R10 for balanced output operation.
LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2
local oscillator inputs. LOSEL selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled
when the LOSEL jumper is removed. Jumper can be removed to
allow LOSEL interface to be exercised using external logic generator.
PWDN Interface. When the PWDN 2-pin shunt is inserted, the
ADL5356 is powered down. When R19 is open, it pulls the PWDN
logic low and enables the device. Jumper can be removed to allow
PWDN interface to be excercised using an external logic generator.
Grounding the PWDN pin is allowed during nominal operation but
is not permitted when supply voltages exceed 3.3 V.
Bias Control. R16 and R17 form a voltage divider to provide a 3 V for
logic control, bypassed to ground through C34. R7, R8, R11, R12, R13,
and R14 provide resistor programmability of VGS0, VGS1, and VGS2.
Typically, these nodes can be hardwired for nominal operation.
Grounding these pins is allowed for nominal operation. R2 and R5 set
the bias point for the internal LO buffers. R1 and R4 set the bias point
for the internal IF amplifiers. L3 and L6 are external inductors used to
improve isolation and common-mode rejection.
Rev. 0 | Page 22 of 24
Figure 56. Evaluation Board Bottom Layer
Default Conditions
C10 = 4.7 μF (Size 3216),
C1, C8, C12, C21 = 150 pF (Size 0402),
C22, C23, C24, C25, C26 = 10 pF (Size 0402),
C13, C15, C18 = 0.1 μF (Size 0402)
C2, C7 = 10 pF (Size 0402),
C3, C6 = 0.01 μF (Size 0402),
C9, C11 = 1.8 pF (Size 0402),
Z2, Z4 = 15 nH,
Z1, Z3 = open (Size 0402)
C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402),
C27, C28 = 150 pF (Size 0402),
T1, T2 = TC4-1T+ (Mini-Circuits),
L1, L2, L4, L5 = 330 nH (Size 0805),
R3, R6, R9, R10 = 0 Ω (Size 0402)
C14, C16 = 10 pF (Size 0402),
R15 = 10 kΩ (Size 0402),
LOSEL = 2-pin shunt
R19 = 10 kΩ (Size 0402),
PWDN = 2-pin shunt
R1, R4 = 1.3 kΩ (Size 0402),
R2, R5 = 1 kΩ (Size 0402),
L3, L6 = 0 Ω (Size 0603),
R12, R13, R14 = open (Size 0402),
R7, R8, R11 = 0 Ω (Size 0402),
R16 = 10 kΩ (Size 0402),
R17 = 15 kΩ (Size 0402),
C34 = 1 nF (Size 0402)