CS8401A-IP ETC [List of Unclassifed Manufacturers], CS8401A-IP Datasheet - Page 11

• Manufacturer Part Number: CS8401A-IP
• Description: Digital Audio Interface Transmitter
• Manufacturer: ETC [List of Unclassifed Manufacturers]

MSB last mode, or by restricting the number of
SCK periods between samples to the sample
word length. The 16-, 18-, and 20-bit LSB-last
modes require at least 16, 18, or 20 SCK periods
per sample respectively. As a master, 32 SCK pe-
riods are output per sample.
FSYNC must be derived from MCK via a DSP
using the same clock or by external counters. If
FSYNC moves (jitters) with respect to MCK by
more than 4 MCK periods, the CS8401A may
reset the channel status block and flags. Appen-
dix C contains more information on the
relationship of FSYNC and MCK.
Buffer Memory
In all buffer modes, the status register and con-
trol registers are located at addresses 0-3
DS60F1
SDF
210 (bit)
000
001
010
100
110
FSF
10 (bit)
00
01
10
11
00
01
10
11
MSTR
0
0
0
0
1
1
1
1
Name
MSB First
MSB Last
LSB Last 16
LSB Last 18
LSB Last 20
FSYNC Input
FSYNC Input
FSYNC Input
FSYNC Input
FSYNC Output
FSYNC Output
FSYNC Output
FSYNC Output
MSB
LSB
LSB
LSB
Figure 10. CS8401A Serial Port SDATA and FSYNC Timing
MSB
16 Clocks
16 Clocks
24 bits, incl. Aux
MSB
LSB
32 Clocks
32 Clocks
Left Sample
MSB
24 bits, incl. Aux
MSB
20 Bits
18 Bits
16 Clocks
16 Clocks
LSB
16 Bits
respectively, and the user data is buffered in lo-
cations 4-7. The parallel port can access any
location in the user data buffer at any time; how-
ever, care must be taken not to modify a location
when that location is being read internally. This
internal reading is done through the second port
of the buffer and is done in a cyclic manner.
Reset initializes the internal pointer to
04H (Hex). Data is read from this location and
stored in an 8-bit shift register which is shifted
once per audio sample. (An audio sample is de-
fined as a single channel, not a stereo pair.) The
byte is transmitted LSB first, D0 being the first
bit. After transmitting 8 samples, i.e. 8 user bits,
the address pointer is incremented and the next
byte of user data is loaded into the shift register.
After transmitting all four bytes, 32 audio sam-
MSB
LSB
LSB
LSB
MSB
24 bits, incl. Aux
LSB
MSB
32 Clocks
Right Sample
MSB
24 bits, incl. Aux
32 Clocks
MSB
20 Bits
18 Bits
LSB
16 Bits
CS8401A
MSB
LSB
LSB
LSB
MSB
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