CS8401A-IP ETC [List of Unclassifed Manufacturers], CS8401A-IP Datasheet - Page 12

• Manufacturer Part Number: CS8401A-IP
• Description: Digital Audio Interface Transmitter
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ples, the user read pointer is reset to 04H (Hex)
and the cycle repeats.
Flag 0 in the status register monitors the position
of the internal user data read pointer. When the
first byte, location 04H, is read, flag 0 is set low
and when the third byte, location 06H, is read,
flag 0 is set high. If mask 0 in control register 1
is set, a transition of flag 0 will generate a low
pulse on the interrupt pin. The value of flag 0
indicates which two bytes the part will read next,
thereby indicating which two bytes are free to be
updated.
12
Flag 2
Flag 1
Mode 0
Flag 1
Modes 1 & 2
Flag 0
bit
23
See figure 15
0
0
Preamble
A 0
1
Frame
2
3 4
B 0
3
Aux Data
Figure 11. CS8401A Status Register Flag Timing
4
5
A 1
7 8
6
LSB
7
B 1
(Expanded)
(Expanded)
8
(384 Audio Samples)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Channel Status Byte
A 2
Block
Sub-frame
Flag 1 is mode dependent, changing with buffer
memory configuration, and is discussed in the
individual buffer mode sections.
Flag 2 is set high when byte 0 of the channel
status, address 08H, is read, and set low when
byte 4, address 0BH, is read. Therefore, flag 2
high indicates the part is reading the first four
bytes of channel status, and the last 20 bytes are
free to update. If the interrupt mask bit for flag 2
is set, the rising edge will cause an interrupt in-
dicating the beginning of a channel status block
as shown in Figure 11. Although a falling edge
B 2
Audio Data
Channel Status Data
User Data
Parity Bit
Validity
A 7
MSB
27
28 29 30 31
V U C P
B 7
CS8401A
0
1
DS60F1