CS8401A-IP ETC [List of Unclassifed Manufacturers], CS8401A-IP Datasheet - Page 15

• Manufacturer Part Number: CS8401A-IP
• Description: Digital Audio Interface Transmitter
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Buffer-Read and Interrupt Timing
As mentioned previously in the buffer mode sec-
tions, conflicts between externally writing to the
buffer ram and the CS8401A internally reading
bytes of ram for transmission may be averted by
using the flag levels to avoid the section cur-
rently being addressed by the part. Interrupts
occur at flag edges indicating the exact byte that
the part is currently reading. Utilizing INT along
with the flags, the byte currently being read by the
part can be avoided allowing access to all other
bytes instead of just a section. Figure 15 illustrates
the timing between flags, INT, and the internal
DS60F1
Right C.S. Ad.
Right C.S. Ad.
User Address
Left C.S. Ad.
Left C.S. Ad.
IMCK
Flag 2
Flag 1
Flag 0
C.S. Byte
Flags 0 & 1
RAM Read
Flag 1
Flag 0
(128Fs)
Flag 2
TXP
TXN
INT
08
10
08
10
04
0
1
05
2
C
09
11
06
Figure 14. CS8401A Buffer Memory Read Sequence - MODE 2
3
0B 0C
13 14
4
Figure 15. RAM/Buffer-Read and Interrupt Timing
07
5
0A
12
04
6
P
7
0F 0C
17 14
05
8
(384 Audio Samples)
0B
13
06
9
(Expanded)
10
07
Block
11
0F 0C
17 14
reading of the buffer for transmission. The mas-
ter clock IMCK is shown as 128 Fs. Other
MCK frequencies are initially divided to obtain
128 Fs, defined as IMCK (internal MCK),
which is then used for all internal timing, so the
timing in Figure 15 is valid for all MCK fre-
quencies. When the parity bit (P) is transmitted, a
transition on a flag causes INT to go low if the
appropriate mask bit is set. Concurrently, the part
starts reading from the internal buffer. Writing to
the buffer ram location being read by the part
should be avoided while the internal "ram read"
signal is high.
12
13
14
Transmit Preamble
15
0F 0C
17 14
16
17
18
(Addresses are in Hex)
19
0F 0C
17 14
20
21
CS8401A
22
23
0F 08
14 10
0
1
15