CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 14

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

in both channel A and channel B, one bit per frame.
Like the user-data buffer, the parallel port can ac-
cess any location in this buffer at any time. The
transmitter section reads this buffer in a cyclic non-
destructive manner and stores the byte in an 8-bit
shift register that is shifted once per two transmit-
ted audio samples (once per frame).
Flag1 in the status register can be used to monitor
the channel status buffer. In mode 0, flag 1 is set
low when byte 0, location 08H, is read and set high
when byte 16, location 18H, is read. If mask 1 in
control register 1 is set, a transition on flag 1 will
generate a pulse on the interrupt pin. Figure 12 il-
lustrates the memory read sequence for buffer
mode 0 along with the flag timing. The arrows on
the flags indicate an interrupt if the appropriate
mask bit is set. Flag 0 can cause an interrupt on ei-
ther edge, which is shown only in the expanded
portion of the Figure for clarity. The expanded sec-
tion also shows that the user buffer is reread when
location 0AH of the channel status is read.
Buffer Mode 1
In buffer mode 1, eight bytes are allocated for chan-
nel status data and 16 bytes for auxiliary data as
shown in Figure 5. The channel status buffer, loca-
14
C.S. Address
User Address
C.S. Byte
C.S. Address
Flag 2
Flag 1
Flag 0
Flag 0
08
08
04
0
1
05
2
09
06
Figure 12. CS8403A Buffer Momory Read Sequence - MODE 0
0B
3
0C
4
07
5
0A
04
6
7
05
8
0B
06
(384 Audio Samples)
(Expanded)
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
07
Block
tions 08H to 0FH, is divided into two sections. The
first four locations always contain the first four
bytes of channel status, identical to mode 0, and are
read once per channel status block. The second four
locations, addresses 0CH to 0FH, provide a cyclic
buffer for the last 20 bytes of channel status data.
Similar to mode 0, transmitted channel status data
will be the same for channel A and channel B (one
channel status bit per frame). Flag 1 and flag 2 can
be used to monitor this buffer. Flag 1 is set low
when byte 0 of channel status data, location 08H, is
read and is toggled when every other byte is read.
As shown in Figure 13, flag 2 is set high when byte
0, location 08H, is read and set low when byte 4, lo-
cation 0CH, is read. Flag 2 determines whether the
channel status pointer is reading the first four-byte
section or the second four-byte section, while flag
1 indicates which two bytes of the section are free
to update.
The auxiliary data buffer, locations 10H to 1FH, is
read in a cyclic manner similar to the data buffer;
however, four auxiliary data bits are transmitted
per audio sample (sub-frame). Since the auxiliary
buffer must be read four times as often as the user
data buffer and is four times as large, flag 0 can be
used to monitor both.
(Addresses are in Hex)
CS8403A CS8404A
DS239PP1
1F
08
0
1