CS8403A-CS CIRRUS [Cirrus Logic], CS8403A-CS Datasheet - Page 23

• Manufacturer Part Number: CS8403A-CS
• Description: 96KHZ DIGITAL AUDIO TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

When FSYNC is a word clock (Format 2), CBL is
sampled when left C, U, V are sampled. When
FSYNC is Left/Right, CBL is sampled when left C,
U, V are sampled. The channel status block bound-
ary is reset when CBL transitions from low to high
(based on two successive samples of CBL). MCK
for the CS8404A is normally expected to be 128
times the sample frequency, in the transparent
mode MCK must be 256 Fs.
Professional Mode
Setting PRO low places the CS8404A in profes-
sional mode as shown in Figure 19. In professional
mode, channel status bit 0 is transmitted as a one
and bits 1, 2, 3, 4, 6, 7, and 9 can be controlled via
dedicated pins. The pins are actually the inverse of
the identified bit. For example, tying the C1 pin
low places a one in channel status bit 1. As shown
in the Application Note (AN22), Overview of AES/
EBU Digital Audio Interface Data Structures, C1
DS239PP1
FSYNC
SDATA
TRNPT
SCK
C
U
V
PRO
8
6
7
10
11
9
24
2
Registers
EM0
14
EM1
13
C1
Figure 19. CS8404A Block Diagram - Professional Mode
3
M2 M1 M0
C6
23 22 21
Serial
Logic
Port
4
C7
1
C9
12
Preamble
Validity
C Bits
U Bits
Audio
Parity
CRC
Aux
indicates audio/non-audio; C6 and C7 determine
the sample frequency; and C9 allows the encoded
channel mode to be stereophonic. EM1 and EM0
determine emphasis and encode C2, C3, C4 as
shown in Table 4. The dedicated channel status
pins are read at the appropriate time and are logi-
cally OR’ed with data input on the channel status
port, C. In Transparent Mode, these dedicated
channel status pins are ignored and channel status
bits are input at the C pin.
EM1
0
0
1
1
Mux
Table 4. Emphasis Encoding
EM0
0
1
0
1
CBL
Encoder
Biphase
Timing
15
Mark
CS8403A CS8404A
MCK
C2
5
1
1
1
0
Driver
Line
C3
1
1
0
0
20
17
16
TXP
TXN
RST
C4
1
0
0
0
23