CS8405A-IZ CIRRUS [Cirrus Logic], CS8405A-IZ Datasheet - Page 13

• Manufacturer Part Number: CS8405A-IZ
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

mode operation. The CS8405A is set to mono
mode by the MMT control bit.
In mono mode, the input port will run at the audio
sample rate (Fs), while the AES3 transmitter frame
rate will be at Fs/2. Consecutive left or right chan-
nel serial audio data samples may be selected for
transmission on the A and B sub-frames, and the
channel status block transmitted is also selectable.
DS469PP4
TCBL
In or Out
TCBL
In or Out
VLRCK
SDIN
Input
VLRCK
SDIN
Input
TXP(N)
Output
TXP(N)
Output
TXP(N)
Output
VCU
Input
U
Input
VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.
VLRCK duty cycle is 50%.
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.
If the serial audio input port is on slave mode and TCBL is an output, then VLRCK=ILRCK if SILRPOL=0 and
VLRCK= ILRCK if SILRPOL =1.
If the serial audio input port is in master mode and TCBL is an input, then VLRCK=ILRCK if SILRPOL=0 and
VLRCK= ILRCK if SILRPOL =1.
Tth
Tth
* Assume MMTLR = 0
Z
* Assume MMTLR = 1
Z
Z
Figure 7. AES3 Transmitter Timing for C, U, and V Pin Input Data
Data [4]
Data [4]
Data [0]
Tsetup
Data [1]*
VCU[0]
Data [0]*
Y
Thold
Data [5]
Data [5]
Data [1]
AES3 Transmitter in Mono mode
AES3 Transmitter in Stereo mode
VCU[1]
U[0]
Y
X
Y
Data [6]
Data [6]
Data [2]
Using mono mode is only necessary if the incom-
ing audio sample rate is already at 96 kHz and con-
tains both left and right audio data words. The
“mono mode” AES3 output stream may also be
achieved by keeping the CS8405A in normal stereo
mode, and placing consecutive audio samples in
the left and right positions in an incoming 48 kHz
word rate data stream.
Data [3]*
Data [2]*
VCU[2]
Y
Data [7]
Data [7]
Data [3]
VCU[3]
Tth > 3OMCK if TCBL is Input
Tth > 3OMCK if TCBL is Input
Tsetup => 7.5% AES3 frame time
Thold = 0
Tsetup => 15% AES3 frame time
Thold = 0
U[2]
X
X
X
Data [8]
Data [8]
Data [4]
Data [5]*
Data [4]*
VCU[4]
CS8405A
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