CS8405A-CS Cirrus Logic Inc, CS8405A-CS Datasheet
CS8405A-CS
Specifications of CS8405A-CS
Available stocks
Related parts for CS8405A-CS
CS8405A-CS Summary of contents
Page 1
... Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. ORDERING INFORMATION CS8405A-CS 28-pin SOIC CS8405A-CZ 28-pin TSSOP CS8405A-IS CS8405A-IZ CDB8415A VD+ C & ...
Page 2
... SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 CS8405A DS469PP4 ...
Page 3
... Channel Status Data Buffer Control (12h) ...................................................................... 22 8.13 User Data Buffer Control (13h) ....................................................................................... 23 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 23 8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ................................................. 23 9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 24 10. HARDWARE MODE ............................................................................................................. 26 10.1 Channel Status, User and Validity Data ........................................................................ 26 10 ...
Page 4
... Notes: 3. Transient currents 100 mA will not cause SCR latch-up. 4 (DGND = 0 V, all voltages with respect to Symbol VD+ VL+ VD VD Reset high, VD+ Reset high, VL Reset high, VL (Note 2) (DGND = 0V, all voltages with respect to ground) Symbol VD/VL+ (Note stg CS8405A Min Typ Max Units 4.5 5.0 5.5 V 2. ...
Page 5
... VD+ = 5V±10%, VL+ = 3/5V ±5/10%) A Symbol V IH (Note mA mA) OL =0.4V (Max -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs: A Symbol CS8405A Min Typ Max 2.0 - (VL+) + 0.3 -0.3 - 0.4/0 0.4 (VL ±1 ±10 (VL+) - 0.7 (VL 0.4 ...
Page 6
... VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs: A Symbol (Note (Note (Note 5) t smd (Note 6) t lmd (Note 7) t sckw t sckl t sckh (Note 5,6,8) t lrckd (Note 5,6,9) t lrcks ILRCK (input) ISCLK (input) t lmd SDIN Figure 2. Audio Port Slave Mode and Data Input Timing CS8405A Min Typ Max ...
Page 7
... CCLK CDIN CDOUT DS469PP4 = -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs: A Symbol (Note 10 (Note 11 (Note 12) (Note 12) t scl t sch dsu Figure 3. SPI Mode timing CS8405A Min Typ Max 0 - 6.0 sck 1 csh css scl sch dsu ...
Page 8
... C protocol and is supported only at 5V mode. Repeated Start t high t t sud t sust hdd Figure 4. Two-Wire Mode timing CS8405A Min Typ Max Units - - 100 kHz µs 4 µs 4 µs 4 µs 4 µs 4 µ ...
Page 9
... DS469PP4 µ µ 0.1 F 0.1 F + TXP CS8405A TXN RXP SDA/CDOUT ILRCK AD0/CS ISCLK SCL/CCLK SDIN AD1/CDIN AD2 U OMCK INT NC1 H/S NC2 NC3 DGND2 NC4 DGND3 NC5 RST TCBL DGND4 DGND CS8405A +5V Supply AES3/ Cable SPDIF Interface Equipment Microcontroller 9 ...
Page 10
... GENERAL DESCRIPTION The CS8405A is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter- face standards. The CS8405A accepts audio, chan- nel status and user data, which is then multiplexed, encoded, and driven onto a cable. ...
Page 11
... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit Figure 6. Serial Audio Input Example Formats DS469PP4 Left LSB MSB LSB MSB Left MSB LSB SISF* SIRES[1:0]* SIJUST CS8405A Right LSB MSB Right LSB MSB Right MSB LSB SIDEL* SISPOL* SILRPOL MSB ...
Page 12
... CS8405A. The user can manually access the internal storage or configure the CS8405A to run in one of several automatic modes. “Appendix B: Channel Status and User Data Buffer Management” on page 34 provides detailed de- scriptions of each automatic mode and describes methods of manually accessing the storage areas ...
Page 13
... The CS8405A is set to mono mode by the MMT control bit. In mono mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate will be at Fs/2. Consecutive left or right chan- nel serial audio data samples may be selected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable ...
Page 14
... AD0 bit address state. 6.1 SPI Mode In SPI mode the CS8405A chip select signal, CCLK is the control port bit clock (input into the CS8405A from the microcontroller); CDIN is the input data line from the microcontroller; and CD- OUT is the output data line to the microcontroller ...
Page 15
... Each byte is sepa- rated by an acknowledge bit, ACK, which is output from the CS8405A after each input byte is read. The ACK bit is input to the CS8405A from the mi- crocontroller after each transmitted byte. The Two- Wire Mode is compatible with the I 6 ...
Page 16
... MAP6 INCR - Auto Increment Address Control Bit Default = ‘0’ Disable 1 - Enable MAP6:MAP0 - Register Address Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8405A ...
Page 17
... Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ TCBL is an input 1 - TCBL is an output DS469PP4 MUTEAES 0 CS8405A INT1 INT0 TCBLD 17 ...
Page 18
... AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive AESBP - AES3 bypass mode selection Default = ‘0’ Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input AESBP 0 0 CS8405A MMT MMTCS MMTLR DS469PP4 ...
Page 19
... This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var- ious Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low current consumption, state. Default = ‘0’ ...
Page 20
... When TCBL is an input, this bit will go high on receipt of a new TCBL signal. EFTC - C-buffer transfer interrupt. The source for this bit is true during the buffer transfer in the C bit buffer management process CS8405A 2 S mode EFTC 0 DS469PP4 ...
Page 21
... INT pin and the status register mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 2 register. This register defaults to 00h. DS469PP4 CS8405A EFTU EFTCM EFTC1 0 0 EFTC0 EFTUM ...
Page 22
... EFTCI - C-data buffer transfer inhibit bit. Default = ‘0’ Allow C-data buffer transfers 1 - Inhibit C-data buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ One byte mode 1 - Two byte mode BSEL 0 0 CS8405A EFTU1 0 0 EFTU0 EFTCI CAM 0 DS469PP4 ...
Page 23
... Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8405A I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID3 code for the CS8405A. Permanently set to 0110 VER3:0 - CS8405A revision level. Revision A is coded as 0001 DS469PP4 UBM1 5 ...
Page 24
... VL Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal states are RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important ...
Page 25
... Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation H/S of the CS8405A, and the method of accessing Channel Status and User bit data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation, and access to CS and U data is provided by dedicated pins ...
Page 26
... HARDWARE MODE The CS8405A has a hardware mode that allows the use of the device without a microcontroller. Hard- ware mode is selected by connecting the H/S pin to VL+. The flexibility of the CS8405A is necessarily limited in hardware mode. Various pins change function as described in the hardware mode pin de- scription section ...
Page 27
... Table 4. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode DS469PP4 Function 0 Serial Input Format IF1 - Left Justified 1 2 Serial Input Format IF2 - Serial Input Format IF3 - Right Justified, 24- bit data Serial Input Format IF4 - Right Justified, 16- 1 bit data SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL CS8405A ...
Page 28
... DGND 22 9 Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal states are RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important ...
Page 29
... Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation H/S of the CS8405A, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode pro- vides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. This pin should be permanently tied to VL+ or DGND ...
Page 30
... APPLICATIONS 12.1 Reset, Power Down and Start-up When RST is low, the CS8405A enters a low pow- er mode and all internal states are reset, including the control port and registers, and the outputs are disabled. When RST is high, the control port be- comes operational and the desired settings should be loaded into the control registers ...
Page 31
... JEDEC #: MS-013 Controlling Dimension is Millimeters CS8405A MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 ...
Page 32
... BSC 9.60 BSC 0.256 6.30 0.177 4. 0.024 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8405A 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6 ...
Page 33
... AES3 transmitter to cables and fiber-optic components. 14.1 AES3 Transmitter External Components The output drivers on the CS8405A are designed to drive both the professional and consumer interfac- es. The AES3 specification for professional/broad- cast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω ...
Page 34
... If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8405A, and does not have to be written into the last byte of the block by the host microcontroller. This is also true if the channel sta- tus data is entered serially through the COPY/C pin when the part is in hardware mode ...
Page 35
... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8405A to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
Page 36
...