CS8405A-IS CIRRUS [Cirrus Logic], CS8405A-IS Datasheet
CS8405A-IS
Related parts for CS8405A-IS
CS8405A-IS Summary of contents
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... Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer or automotive audio systems. ORDERING INFORMATION CS8405A-CS CS8405A-CZ CS8405A-CZZ, Lead Free CS8405A-IS CS8405A-IZ CDB8415A C & U bit AES3 Data S/PDIF Buffer Encoder Control Port & ...
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... Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)....................................... 22 8.12 Channel Status Data Buffer Control (12h) ...................................................................... 23 8.13 User Data Buffer Control (13h) ....................................................................................... 23 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 24 8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ................................................. 24 9. PIN DESCRIPTION - SOFTWARE MODE 10. HARDWARE MODE ............................................................................................................. 27 10.1 Channel Status, User and Validity Data ......................................................................... 27 10 ...
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... Figure 15. Flowchart for Writing the E Buffer ................................................................................ 35 LIST OF TABLES Table 1. Control Register Map Summary...................................................................................... 17 Table 2. Hardware Mode COPY/C and ORIG pin functions ......................................................... 27 Table 3. Hardware Mode Serial Audio Port Format Selection ...................................................... 28 Table 4. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode28 Table 5. Revision History .............................................................................................................. 37 DS469F2 CS8405A 3 ...
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... Symbol VD+ (Note 1) VL+ ‘-CS’ & ‘-CZ’ ‘-IS’ & ‘-IZ’ (DGND = 0 V; all voltages with respect Operation beyond these Symbol VD+,VL+ (Note stg CS8405A Min Typ Max Units 4.5 5.0 5.5 V 2.85 3.3 or 5.0 5.5 V -10 - +70 °C -40 - +85 Min ...
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... V; all voltages with respect to 0 V.) Symbol ( VL+ = 5.0 V) (15 VL+ = 3 VL+ = 5.0 V) (15 VL (Note =0.4 V (Max). IL Symbol VL TXP VL+ = 3.3 V VL TXN VL+ = 3.3 V CS8405A Min Typ Max Units µ µ µ 6 30 46.5 - ...
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... This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed pF) L Symbol = 20 pF) L Symbol (Note (Note (Note 6) t smd (Note 7) t lmd (Note 8) t sckw t sckl t sckh (Note 6,7,9) t lrckd t lrcks CS8405A Min Typ Max Units µs 200 - - 4.1 - 55.3 MHz 7 3.1 - 41.5 MHz 10 2.0 - 27.7 MHz 14 ...
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... ISCLK (output) ILRCK (output) t smd t OMCK (input) Figure 1. Audio Port Master Mode Timing DS469F2 ILRCK (input) t lrckd ISCLK (input) lmd SDIN Figure 2. Audio Port Slave Mode and Data Input Timing CS8405A lrcks sckh sckl t sckw ...
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... MHz. sck CS t css CCLK CDIN CDOUT pF) L Symbol (Note 11 (Note 12 (Note 13) (Note 13) t scl t sch dsu Figure 3. SPI Mode timing CS8405A Min Typ Max 0 - 6.0 sck 1 csh css scl sch dsu ...
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... L Symbol f scl t buf t hdst t low t high t sust (Note 15) t hdd t sud susp Repeated Start t high t t sud t sust hdd I²C Figure 4. Mode timing CS8405A Min Typ Max Units - - 100 kHz µs 4 µs 4 µs 4 µs 4 µs 4 µ 250 - - ...
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... Figure 5. Recommended Connection Diagram for Software Mode 10 µ µ 0.1 F 0 TXP CS8405A TXN RXP SDA/CDOUT ILRCK AD0/CS ISCLK SCL/CCLK SDIN AD1/CDIN AD2 U OMCK INT NC1 H/S NC2 NC3 DGND2 NC4 DGND3 NC5 RST TCBL DGND4 DGND CS8405A +3 +5.0 V Supply AES3/ Cable SPDIF Interface Equipment Microcontroller DS469F2 ...
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... GENERAL DESCRIPTION The CS8405A is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter- face standards. The CS8405A accepts audio, channel status and user data, which is then multi- plexed, encoded, and driven onto a cable. ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit 12 Left LSB MSB LSB MSB Left MSB LSB SISF* SIRES[1:0]* SIJUST Figure 6. Serial Audio Input Example Formats CS8405A Right LSB MSB Right LSB MSB Right MSB LSB SIDEL* SISPOL* SILRPOL MSB ...
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... In this “mono mode”, two AES3 cables are needed for stereo data transfer. The CS8405A of- fers mono mode operation. The CS8405A is set to mono mode by the MMT control bit. In mono mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate will be at Fs/2 ...
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... Data [5] Data [6] Data [1] X Data [2] Y AES3 Transmitter in Stereo mode U[0] Data [5] Data [6] Y Data [2]* Y Data [3]* AES3 Transmitter in Mono mode CS8405A VCU[3] VCU[4] Data [7] Data [8] Data [3] X Data [4] Tsetup => 7.5% AES3 frame time Thold = 0 Tth > 3OMCK if TCBL is Input U[2] Data [7] Data [8] X Data [4]* ...
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... AD0 bit address state. 6.1 SPI Mode In SPI mode the CS8405A chip select sig- nal, CCLK is the control port bit clock (input into the CS8405A from the microcontroller); CDIN is the in- put data line from the microcontroller; and CDOUT is the output data line to the microcontroller ...
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... VL+ or DGND as desired. The upper four bits of the seven-bit address field are fixed at 0010. To com- municate with a CS8405A, the chip address field, which is the first byte sent to the CS8405A, should match 0010 followed by the settings of AD2, AD1, and AD0. The eighth bit of the address is the R/W bit ...
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... INCR - Auto Increment Address Control Bit Default = ‘0’ Disable 1 - Enable MAP6:MAP0 - Register Address Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8405A. DS469F2 ...
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... Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data MUTEAES CS8405A INT1 INT0 TCBLD MMT MMTCS MMTLR DS469F2 ...
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... This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low current consumption, state. Default = ‘0’ ...
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... SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high SIRES0 SIJUST CS8405A SIDEL SISPOL SILRPOL DS469F2 ...
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... INT pin or the status register. The bit positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h. DS469F2 CS8405A EFTC EFTU EFTCM 0 21 ...
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... High or Low) only depends on the INT[1:0] bits. These registers default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved CS8405A EFTC1 0 0 EFTC0 EFTUM EFTU1 0 0 EFTU0 0 0 DS469F2 ...
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... Reserved 11 - Reserved EFTUI - U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ Allow U-data buffer transfers 1 - Inhibit U-data buffer transfer DS469F2 BSEL UBM1 CS8405A EFTCI CAM UBM0 0 EFTUI 23 ...
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... Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8405A I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID3 code for the CS8405A. Permanently set to 0110 VER3:0 - CS8405A revision level. Revision A is coded as 0001 ID1 ID0 VER3 CS8405A ...
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... DGND4 7 9 Reset ( Input ) - When RST is low, the CS8405A enters a low power mode and all internal RST states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important ...
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... SCL/CCLK 28 Control Port Clock ( Input ) - Serial control interface clock and is used to clock control data bits into and out of the CS8405A. In I²C mode, SCL requires an external pull-up resistor to VL+. 2 Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) ( Input falling edge on this pin AD0/CS puts the CS8405A into SPI control port mode ...
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... HARDWARE MODE The CS8405A has a hardware mode that allows the use of the device without a microcontroller. Hardware mode is selected by connecting the H/S pin to VL+. The flexibility of the CS8405A is neces- sarily limited in hardware mode. Various pins change function as described in the hardware mode pin description section. ...
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... Serial Input Format IF2 - I²S 0 Serial Input Format IF3 - Right Justified, 24-bit data 1 Serial Input Format IF4 - Right Justified, 16-bit data SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL CS8405A DS469F2 ...
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... DGND4 9 Reset ( Input ) - When RST is low, the CS8405A enters a low power mode and all internal states are RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important ...
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... Channel Status bit in the outgoing AES3 data stream. ORIG 28 ORIG Channel Status Bit Control ( Input ) - In hardware mode A (CEN = 0), the ORIG and COPY/C pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2. 30 CS8405A DS469F2 ...
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... Extensive use of power and ground planes, ground plane fill in unused areas and surface mount de- coupling capacitors are recommended. Decou- pling capacitors should be mounted on the same side of the board as the CS8405A to minimize in- ductance effects, and all decoupling capacitors should be as close to the CS8405A as possible. 12.4 ...
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... L 0.016 ∝ 0° INCHES NOM MAX 0.098 0.104 0.008 0.012 0.017 0.020 0.011 0.013 0.705 0.713 0.295 0.299 0.050 0.060 0.407 0.419 0.026 0.050 4° 8° JEDEC #: MS-013 Controlling Dimension is Millimeters CS8405A MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 0.32 17.70 17.90 18.10 7.40 7.50 7.60 1.02 1.27 1.52 10 ...
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... SEATING PLANE SIDE VIEW NOM MAX MIN -- 0.47 -- 0.004 0.006 0.05 0.035 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.024 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8405A 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6.50 4.40 4.50 0.65 BSC -- 0.60 0.75 4° 8° ∝ 2 ...
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... AES3 Transmitter External Components The output drivers on the CS8405A are designed to drive both the professional and consumer inter- faces. The AES3 specification for profession- al/broadcast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω ...
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... If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8405A, and does not have to be written into the last byte of the block by the host microcontroller. This is also true if the channel sta- tus data is entered serially through the COPY/C pin when the part is in hardware mode ...
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... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8405A to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
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... Philips I²C Patent Rights to use those components in a standard I²C system. DS469F2 Changes 1st Preliminary Release 2nd Preliminary Release 3rd Preliminary Release 4th Preliminary Release 5th Preliminary Release Final Release Added lead-free device ordering information. Table 5. Revision History www.cirrus.com CS8405A 37 ...