CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 17

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

6. CONTROL PORT DESCRIPTION AND
The control port is used to access the registers, al-
lowing the CS8415A to be configured for the de-
sired operational modes and formats. In addition,
Channel Status and User data may be read
through the control port. The operation of the con-
trol port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid
potential interference problems, the control port
pins should remain static if no operation is re-
quired.
The control port has 2 modes: SPI and I
CS8415A acting as a slave device. SPI mode is
selected if there is a high to low transition on the
AD0/CS pin, after the RST pin has been brought
high. I
AD0/CS pin to VL+ or DGND, thereby permanently
selecting the desired AD0 bit address state.
6.1
In SPI mode, CS is the CS8415A chip select sig-
nal, CCLK is the control port bit clock (input into the
CS8415A from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller. Data is
clocked in on the rising edge of CCLK and out on
the falling edge.
Figure 8 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and
C C L K
CS
C D IN
C D O U T
TIMING
2
SPI Mode
C mode is selected by connecting the
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
0010000
C H IP
High Impedance
R/W
M A P
Figure 8. Control Port Timing in SPI Mode
MSB
b y te 1
2
C, with the
DATA
b y te n
LSB
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which should be low to write. The
next eight bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next eight bits are the
data which will be placed into the register designat-
ed by the MAP. During writes, the CDOUT output
stays in the Hi-Z state. It may be externally pulled
high or low with a 47 KΩ resistor, if desired.
There is a MAP auto increment capability, enabled
by the INCR bit in the MAP register. If INCR is a ze-
ro, the MAP will stay constant for successive read
or writes. If INCR is set to a 1, the MAP will autoin-
crement after each byte is read or written, allowing
block reads or writes of successive registers.
To read a register, the MAP has to be set to the
correct address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read,
bring CS low, send out the chip address and set
the read/write bit (R/W) high. The next falling edge
of CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
6.2
In I
is clocked into and out of the part by the clock,
2
A D D R E S S
C mode, SDA is a bidirectional data line. Data
C H IP
0010000
I
2
C Mode
R/W
MSB
LSB MSB
CS8415A
LSB
17