CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 21

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

8.3
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
8.4
SOMS
7
0
7
Clock Source Control (04h)
Serial Audio Output Port Data Format (06h)
MUX2:0 - 7:1 S/PDIF Input Multiplexer Select Line Control
RUN - Controls the internal clocks, allowing the CS8415A to be placed in a “powered down”, low
current consumption, state.
SOMS - Master/Slave Mode Selector
SOSF - OSCLK frequency (for master mode)
SORES1:0 - Resolution of the output data on SDOUT
SOSF
RUN
001 - RXP1
010 - RXP2
011 - RXP3
100 - RXP4
101 - RXP5
110 - RXP6
111 - Reserved
1 - Serial audio output port is in master mode
1 - 128*Fs
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits,
the time slot normally occupied by the P bit is used to indicate the location of the block start,
Default = ‘000’
000 - RXP0
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8415A to begin
Default = ‘0’
0 - Serial audio output port is in slave mode
Default = ‘0’
0 - 64*Fs
Default = ‘00’
00 - 24-bit resolution
6
6
operational, allowing registers to be read or changed. Reading and writing the U and C data
buffers is not possible. Power consumption is low.
operation. All input clocks should be stable in frequency and phase when RUN is set to 1.
SORES1
5
5
0
SORES0
4
0
4
SOJUST
3
0
3
SODEL
2
2
0
SOSPOL
1
0
1
CS8415A
SOLRPOL
0
0
0
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