CS8415A-IZ CIRRUS [Cirrus Logic], CS8415A-IZ Datasheet - Page 40

• Manufacturer Part Number: CS8415A-IZ
• Description: 96 kHz DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: CIRRUS [Cirrus Logic]

16. APPENDIX C: PLL FILTER
16.1 General
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.
Figure 17 is a simplified diagram of the PLL in
these parts. When the PLL is locked to an AES3 in-
put stream, it is updated at each preamble in the
AES3 stream. This occurs at twice the sampling
frequency, F
it is updated at F
doesn’t affect jitter.
There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been de-
signed to have good jitter attenuation characteris-
tics, as shown in Figure 19. In addition, the PLL
has been designed to only use the preambles of
40
S
INPUT
. When the PLL is locked to ILRCK,
S
so that the duty cycle of the input
and Charge Pump
Comparator
Phase
÷N
Figure 17. PLL Block Diagram
Cfilt
Rfilt
the AES3 stream to provide lock update informa-
tion to the PLL. This results in the PLL being im-
mune to data dependent jitter affects because the
AES3 preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of
input sample rates with no external component
changes. If the sample rate of the input subse-
quently changes, for example in a varispeed appli-
cation, the PLL will only track up to ±12.5% from
the nominal center sample rate. The nominal cen-
ter sample rate is the sample rate that the PLL first
locks onto upon application of an AES3 data
stream or after enabling the CS8415A clocks by
setting the RUN control bit. If the 12.5% sample
rate limit is exceeded, the PLL will return to its wide
lock range mode and re-acquire a new nominal
center sample rate.
Crip
VCO
RMCK
CS8415A