M35080-BN3T STMICROELECTRONICS [STMicroelectronics], M35080-BN3T Datasheet - Page 6

• Manufacturer Part Number: M35080-BN3T
• Description: 8 Kbit Serial SPI Bus EEPROM With Incremental Registers
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M35080
Figure 6. RDSR: Read Status Register Sequence
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is execut-
ed, after completion of the write cycle. On the oth-
er hand, the two read-only bits (WEL, WIP) are
dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit
to detect the end of the internal write cycle.
The Comparator bit (INC) indicates if the new val-
ue written in the 16 first word is lower ‘1’ or higher
‘0’ than the previous stored value.
The UV bit indicates if the memory chip has been
erased.
Write Status Register (WRSR)
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eight bits of
the status register have been latched-in, the inter-
nal Write cycle is triggered by the rising edge of
the S line. This must occur after the falling edge of
Figure 7. WRSR: Write Status Register Sequence
6/18
S
C
D
Q
S
C
D
Q
HIGH IMPEDANCE
0
1
INSTRUCTION
2
3
0
4
1
HIGH IMPEDANCE
INSTRUCTION
5
2
6
3
7
4
MSB
7
8
5
STATUS REG. OUT
6
9 10 11 12 13 14 15
6
5
7
MSB
4
7
8
3
6
the 16
the 17
the internal write sequence is not performed.
The WRSR instruction is used for the following:
The size of the write-protection area applies equal-
ly in SPM and HPM. The BP1 and BP0 bits of the
status register have the appropriate value (see Ta-
ble 7) written into them after the contents of the
protected area of the EEPROM have been written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
9 10 11 12 13 14 15
STATUS REG.
2
to select the size of memory area that is to be
write-protected
to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
5
1
4
th
th
0
clock (as indicated in Figure 7), otherwise
3
clock pulse, and before the rising edge of
MSB
7
2
STATUS REG. OUT
6
1
5
0
4
3
AI01797
2
1
0
MSB
7
AI02031