M35080-BN3T STMICROELECTRONICS [STMicroelectronics], M35080-BN3T Datasheet - Page 9

• Manufacturer Part Number: M35080-BN3T
• Description: 8 Kbit Serial SPI Bus EEPROM With Incremental Registers
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 10. Write Data to Incremental Registers (WRINC)
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
WIP bits. WIP is high during the self-timed write
cycle. When the cycle is completed, the write en-
able latch is reset.
Page Write Operation
A maximum of 32 bytes of data can be written dur-
ing one Write time, t
the same page (see Figure 11). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 31 additional bytes can
be shifted in (and the device is deselected after the
last byte).
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xxxx xxx1 1111) and the clock contin-
ues, the counter rolls over to the first address of
the same page (xxxx xxxx xxx0 0000) and over-
writes any previously written data.
As before, the Write cycle only starts if the S tran-
sition occurs just after the eighth bit of the last data
byte has been received, as shown in Figure 12.
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
S
C
D
S
C
D
W
7
32
, provided that they are all to
0
6
33
1
DATA BYTE 2
5
34
INSTRUCTION
2
4
35 36 37 38 39
3
3
4
2
5
1
6
0
7
15
8
14 13
9 10
16 BIT ADDRESS
correctly formulated commands. The main securi-
ty measures can be summarized as follows:
– The WEL bit is reset at power-up.
– S must rise after the eighth clock count (or mul-
– Accesses to the memory array are ignored dur-
– After execution of a WREN, WRDI, or RDSR in-
– Invalid S transitions are ignored.
3
20 21 22 23 24 25 26 27
tiple thereof) in order to start a non-volatile write
cycle (in the memory array or in the status reg-
ister).
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
struction, the device enters a wait state, and
waits to be deselected.
2
1
0
7
6
DATA BYTE 1
5
4
3
28 29 30
2
1
0
31
AI02146B
M35080
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